CY8C26443 Datasheet, PDF (38/150 Pages) Cypress Semiconductor – Configurable Mixed-Signal Array with On-board Controller

Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
7.1.5 Phase-Locked Loop (PLL) Operation
The Phase-Locked Loop (PLL) function generates the
system clock with crystal accuracy. It is designed to pro-
vide a 23.986 MHz oscillator when utilized with an exter-
nal 32.768 kHz crystal. Although the PLL provides
crystal accuracy it requires time to lock onto the refer-
ence frequency when first starting. After the External
Crystal Oscillator has been selected and enabled, the
following procedure should be followed to enable the
PLL and allow for proper frequency lock:
1. Select a CPU frequency of 3 MHz or less.
2. Enable the PLL.
3. Wait at least 10 ms.
4. Set CPU to a faster frequency, if desired. To do this,
write the bits CPU[2:0] in the OSC_CR0 register.
The CPU frequency will immediately change when
these bits are set.
If the proper settings are selected in PSoC Designer, the
above steps are automatically done in boot.asm.
7.2 System Clocking Signals
There are twelve system-clocking signals that are used
throughout the device. Referenced frequencies are
based on use of 32.768 kHz crystal. The names of these
signals and their definitions are as follows:
Table 39:
Signal
48M
24M
24V1
24V2
32K
CPU
SLP
System Clocking Signals and Definitions
Definition
The direct 48 MHz output from the Internal Main Oscillator.
The direct 24 MHz output from the Internal Main Oscillator.
The 24 MHz output from the Internal Main Oscillator that has been passed through a user-selectable 1
to 16 divider {F = 24 MHz / (1 to 16) = 24 MHz to 1.5 MHz}. The divider value is found in the Oscillator
Control 1 Register (OSC_CR1). Note that the divider will be N+1, based on a value of N written into the
register bits.
The 24V1 signal that has been passed through an additional user-selectable 1 to 16 divider {F = 24
MHz / ((1 to 16) * (1 to 16)) = 24 MHz to 93.7 kHz}. The divider value is found in the Oscillator Control 1
Register (OSC_CR1). Note that the divider will be N+1, based on a value of N written into the register
bits.
The multiplexed output of either the Internal Low Speed Oscillator or the External Crystal Oscillator.
The output from the Internal Main Oscillator that has been passed through a divider that has 8 user
selectable ratios ranging from 1:1 to 1:256, yielding frequencies ranging from 24 MHz to 93.7 kHz.
The 32K system-clocking signal that has been passed through a divider that has 4 user selectable
ratios ranging from 1:2⁶ to 1:2¹⁵, yielding frequencies ranging from 512 Hz to 1 Hz. This signal is used
to clock the sleep timer period.
38
Document #: 38-12010 CY Rev. *B CMS Rev. 3.22
August 18, 2003