W48S101-04 Datasheet, PDF (9/12 Pages) Cypress Semiconductor – Spread Spectrum Motherboard Frequency Generator

PRELIMINARY
W48S101-04
DC Electrical Characteristics: T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%, V_DDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Crystal Oscillator
V_TH
X1 Input Threshold Voltage^[5]
1.5
C_LOAD
Load Capacitance, as seen by
External Crystal^[6]
14
C_IN,X1
X1 Input Capacitance^[7]
Pin X2 unconnected
28
Pin Capacitance/Inductance
C_IN
Input Pin Capacitance
Except X1 and X2
5
C_OUT
Output Pin Capacitance
6
L_IN
Input Pin Inductance
7
Unit
V
pF
pF
pF
pF
nH
AC Electrical Characteristics
T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%,V_DDQ2 = 2.5V± 5%, f_XTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25V
15
15.5 10
10.5 ns
t_H
High Time
Duration of clock cycle above 2.0V
5.2
3.0
ns
t_L
Low Time
Duration of clock cycle below 0.4V
5.0
2.8
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
41
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.25V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max-
200
imum difference of cycle time between
two adjacent cycles.
250 ps
t_SK
Output Skew
Measured on rising edge at 1.25V
175
175 ps
f_ST
Frequency Stabiliza- Assumes full supply voltage reached
3
tion from Power-up
within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
3 ms
Z_o
AC Output Impedance Average value during switching transi-
20
tion. Used for determining series termi-
nation value.
20
Ω
Notes:
5. X1 input threshold voltage (typical) is V_DD/2.
6. The W48S101-04 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal
is 14 pF; this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
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