W48S101-04 Datasheet, PDF (6/12 Pages) Cypress Semiconductor – Spread Spectrum Motherboard Frequency Generator

PRELIMINARY
W48S101-04
Writing Data Bytes
Each bit in the data bytes controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 3–6.
Table 5 details additional frequency selections that are avail-
able through the serial data interface.
Table 6 details the select functions for Byte 3, bits 1 and 0.
Table 4. Data Bytes 3–6 Serial Configuration Map
Affected Pin
Bit Control
Bit(s) Pin No. Pin Name
Control Function
0
1
Data Byte 3
7
--
--
(Reserved)
--
--
6
--
--
SEL_2
Refer to Table 5
5
--
--
SEL_1
Refer to Table 5
4
--
--
SEL_0
Refer to Table 5
3
--
--
BYT0_FS#
Frequency Controlled Frequency Controlled
by external SEL100/ by BYT0 SEL (2:0)
66# pin
2
--
--
(Reserved)
--
--
1–0
--
--
Bit 1 Bit 0 Function (See Table 6 for function details)
0
0 Normal Operation
0
1 Test Mode
1
0 Spread Spectrum on (See Table 5 for frequency and
spread selections. ±0.5% modulation)
1
1 All Outputs Three-stated
Data Byte 4
7
--
--
(Reserved)
--
--
6
23
24/48MHz Clock Output Disable
Low
Active
5
--
--
(Reserved)
--
--
4
--
--
(Reserved)
--
--
3
35
CPU3 Clock Output Disable
Low
Active
2
36
CPU2 Clock Output Disable
Low
Active
1
39
CPU1 Clock Output Disable
Low
Active
0
40
CPU0 Clock Output Disable
Low
Active
Data Byte 5
7
7
PCICLK_F Clock Output Disable
Low
Active
6
17
PCI7
Clock Output Disable
Low
Active
5
16
PCI6
Clock Output Disable
Low
Active
4
14
PCI5
Clock Output Disable
Low
Active
3
13
PCI4
Clock Output Disable
Low
Active
2
11
PCI3
Clock Output Disable
Low
Active
1
10
PCI2
Clock Output Disable
Low
Active
0
8
PCI1
Clock Output Disable
Low
Active
Data Byte 6
7
--
--
(Reserved)
--
--
6
--
--
(Reserved)
--
--
5
44
IOAPIC1 Clock Output Disable
Low
Active
4
45
IOAPIC0 Clock Output Disable
Low
Active
3
--
--
(Reserved)
--
--
2
47
REF2 Clock Output Disable
Low
Active
1
2
REF1 Clock Output Disable
Low
Active
0
1
REF0 Clock Output Disable
Low
Active
Default
0
0
0
0
0
0
00
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
6