W48S101-04 Datasheet, PDF (2/12 Pages) Cypress Semiconductor – Spread Spectrum Motherboard Frequency Generator

PRELIMINARY
W48S101-04
Pin Definitions
Pin Name
Pin No.
CPU0:3
40, 39, 36,
35
PCI1:7
PCI_F
8, 10, 11,
13, 14, 16,
17
7
CPU_STOP#
30
PCI_STOP#
31
SPREAD#
APIC0:1
48MHz
24/48MHz
28
45, 44
22
23
REF0/SEL48#
1
REF1:2
SEL100/66#
SCLK
SDATA
X1
2, 47
25
26
27
4
X2
5
PWR_DWN#
29
VDDQ3
VDDQ2
GND
9, 15, 19,
21, 33, 48
46, 41, 37
3, 6, 12, 18,
20, 24, 32,
34, 38, 43
Pin Type
O
O
O
I
I
I
O
O
O
I/O
O
I
I
I/O
I
I
I
P
Pin Description
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled by
the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.
PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
CPU_STOP# Input: When brought LOW, clock outputs CPU0:3 are stopped LOW
after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH,
clock outputs CPU0:3 start beginning with a full clock cycle (2–3 CPU clock latency).
PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
SPREAD# Input: When brought LOW this pin activates Spread Spectrum clocking.
I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.
48-MHz Output: Fixed clock outputs at 48 MHz. Output voltage swing is controlled
by voltage applied to VDDQ3.
24-MHz or 48-MHz Output: 24-MHz output when pin 1 is strapped through 10-kΩ
resistor to VDDQ3. 48-MHz output when pin 1 is strapped through 10-kΩ resistor to
GND.
I/O Dual Function REF0 and SEL48# pin: During power on, SEL48# input will be
latched, which will set pin 23 to output 24 MHz or 48 MHz. It then reverts to REF0
fixed output.
Fixed 14.318-MHz Outputs 1 through 2: Used for various system applications.
Output voltage swing is controlled by voltage applied to VDDQ3.
Frequency Selection Input: Selects power-up default CPU clock frequency as
shown in Table 1 on page 1.
Clock pin for I²C circuitry.
Data pin for I²C circuitry.
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Down Control: When this input is LOW, device goes into a low-power stand-
by condition. All outputs are actively held LOW while in power-down. CPU and PCI
clock outputs are stopped LOW after completing a full clock cycle (2–3 CPU clock
cycle latency). When brought HIGH, CPU, SDRAM and PCI outputs start with a full
clock cycle at full operating frequency (3 ms maximum latency).
Power Connection: Connect to 3.3V supply.
P
Power Connection: Power supply for APIC0:1 and CPU0:3 output buffers. Connect
to 2.5V.
G
Ground Connections: Connect all ground pins to the common system ground
plane.
2