W48S101-04 Datasheet, PDF (5/12 Pages) Cypress Semiconductor – Spread Spectrum Motherboard Frequency Generator

PRELIMINARY
W48S101-04
Serial Data Interface
The W48S101-04 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions. Upon power-up, the W48S101-04
initializes with default register settings. Therefore, the use of
this serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. Clock device register changes are nor-
mally made upon system initialization, if required. The inter-
face can also be used during system operation for power man-
agement functions. Table 2 summarizes the control functions
of the serial data interface.
Operation
Data is written to the W48S101-04 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held LOW.
and system power. Examples are clock out-
puts to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond the
100- and 66.6-MHz selections that are provided by
the SEL100/66# pin. Frequency is changed in a
smooth and controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency tran-
sition allows CPU frequency change under
normal system operation.
Output Three-state
Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input, inter- Production PCB testing.
nal PLL is bypassed. Refer to Table 4.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
Table 3. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
1
Slave Address 11010010
2
Command
Don’t Care
Code
3
Byte Count
Don’t Care
4
Data Byte 0
Don’t Care
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
Refer to Table 4
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
Byte Description
Commands the W48S101-04 to accept the bits in Data Bytes 3–6 for
internal register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the
W48S101-04 is 11010010. Register setting will not be made if the Slave
Address is not correct (or is for an alternate slave receiver).
Unused by the W48S101-04, therefore bit values are ignored (“don’t
care”). This byte must be included in the data write sequence to maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Unused by the W48S101-04, therefore bit values are ignored (“don’t
care”). This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Refer to Cypress SDRAM drivers.
The data bits in these bytes set internal W48S101-04 registers that con-
trol device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 4, Data Byte Serial Configuration Map.
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