W234 Datasheet, PDF (9/12 Pages) Cypress Semiconductor – Dual Direct Rambus Clock Generator

W234
Table 12. Operating Conditions
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
3.135
3.465
V
T_A
t_CYCLE,IN
t_J,IN
DC_IN
FM_IN
PM_IN[3]
Ambient Operating Temperature
Refclk Input Cycle Time
Input Cycle-to-Cycle Jitter^[2]
Input Duty Cycle over 10,000 Cycles
Input Frequency of Modulation
Modulation Index for Triangular Modulation
Modulation Index for Non-Triangular Modulation
0
70
°C
10
40
ns
–
250
ps
40
60
%t_CYCLE
30
33
kHz
–
0.6
%
–
0.5^[4]
%
t_CYCLE,PD
t_ERR,INIT
DC_IN,PD
t_I,SR
C_IN,PD
∆C_IN,PD
C_IN,CMOS
Phase Detector Input Cycle Time at PCLKM & SYNCLKN
30
Initial Phase error at Phase Detector Inputs
–0.5
Phase Detector Input Duty Cycle over 10,000 Cycles
25
Input Slew Rate (measured at 20%-80% of input voltage) for PCLKM,
1
SYNCLKN, and REFCLK
Input Capacitance at PCLKM, SYNCLKN, and REFCLK^[5]
–
Input Capacitance matching at PCLKM and SYNCLKN^[5]
–
Input Capacitance at CMOS pins (excluding PCLKM, SYNCLKN,
–
and REFCLK)^[5]
100
ns
0.5
t_CYCLE,PD
75
t_CYCLE,PD
4
V/ns
7
pF
0.5
pF
10
pF
V_IL
Input (CMOS) Signal Low Voltage
–
0.3
VDD
V_IH
Input (CMOS) Signal High Voltage
0.7
-
VDD
V_IL,R
Refclk Input Low Voltage
-
0.3
V_DDIR
V_IH,R
Refclk Input High Voltage
0.7
–
V_DDIR
V_IL,PD
Input Signal Low Voltage for PD Inputs and STOP#
–
0.3
V_DDIPD
V_IH,PD
Input Signal High Voltage for PD Inputs and STOP#
0.7
–
V_DDIPD
V_DDIR
Input Supply Reference for REFCLK
1.235
3.465
V
V_DDIPD
Input Supply Reference for PD Inputs
1.235
2.625
V
Notes:
2. Refclk jitter measured at V_DDIR (nom)/2.
3. If input modulation is used: input modulation is allowed but not required.
4. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
5. Capacitance measured at Freq=1 MHz, DC bias=0.9V and V_AC<100 mV.
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