W234 Datasheet, PDF (5/12 Pages) Cypress Semiconductor – Dual Direct Rambus Clock Generator

W234
Table 3. Bypass and Test Mode Selection
Mode
By Pclk
S0 S1 S2 (int.)
CLK
Normal
0 0 0 Gnd
PAClk
Bypass
1 0 0 PLLClk PLLClk
Test
1 1 0 RefClk RefClk
Vendor Test A 0 0 1
-
-
Vendor Test B 1 0 1
-
-
Reserved
111
-
-
Output Test 0 1 X
-
Hi-Z
(OE)
CLK#
PAClk#
PLLClk#
RefClk#
-
-
-
RefClk#
Table 4 shows the logic for selecting the Power-Down mode,
using the PWR_DWN# input signal. PWR_DWN# is active
LOW (enabled when 0). When PWR_DWN# is disabled, the
DRCG is in its normal mode. When PWR_DWN# is enabled,
the DRCG is put into a powered-off state, and the CLK and
CLK# outputs are three-stated.
Table 4. PWR_DWN# Mode Selection
Mode PWR_DWN# CLK
CLK#
Normal
1
PAClk
PAClk#
Power-Down
0
GND
GND
Table of Frequencies and Gear Ratios
Table 5 shows several supported Pclk and Busclk frequencies,
the corresponding A and B dividers required in the DRCG PLL,
and the corresponding M and N dividers in the gear ratio logic.
The column Ratio gives the Gear Ratio as defined Pclk/Synclk
(same as M and N). The column F@PD gives the divided down
frequency (in MHz) at the Phase Detector (φ_D), where
F@PD=PCLK/M=SYNCLK/N.
State Transitions
The clock source has three fundamental operating states.
Figure 4 shows the state diagram with each transition labelled
A through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PWR_DWN#
and STOP#.
In Power-Down mode, the clock source is powered down with
the control signal, PWR_DWN#, equal to 0. The control signals
S0, S1 and S2 must be stable before power is applied to the
device, and can only be changed in Power-Down mode
(PWR_DWN#=0). The reference inputs, VDDIR and VDDIPD,
may remain on or may be grounded during the Power-Down
mode.
The control signals MULT0, MULT1, and MULT2 can be used
in two ways. If they are changed during Power-Down mode,
then the Power-Down transition timings determine the settling
time of the DRCG. However, the MULT0, MULT1, and MULT2
control signals can also be changed during Normal mode.
When the MULT control signals are “hot swapped” in this man-
ner, the MULT transition timings determine the settling time of
the DRCG.
Table 5. Frequencies, Dividers, and Gear Ratios
Pclk
Refclk
Busclk
Synclk
A
B
M
N
Ratio F@PD
67
33
267
67
8
1
2
2
1.0
33
100
50
300
75
6
1
8
6
1.33
12.5
100
50
400
100
8
1
4
4
1.0
25
133
67
267
67
4
1
4
2
2.0
33
133
67
400
100
6
1
8
6
1.33
16.7
V_{DD MTurn-On}
V_DD
Turn-On
G
L
Test
N
J
Normal
B
K
A
F
E
V_DD Turn-On
D
Power-Down
C
Clk Stop
V_DD Turn-On
H
Figure 4. Clock Source State Diagram
5