W234 Datasheet, PDF(4/12 Page) Cypress Semiconductor – Dual Direct Rambus Clock Generator

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W234 Datasheet, PDF (4/12 Pages) Cypress Semiconductor – Dual Direct Rambus Clock Generator

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CY2210-2

CY2210-3

CY2215

W133

W158

Refclk

W159

W161

W167B

W234

PLL

Phase

Align

S0/S1/S2 STOP#

Busclk

W234

RAC

RMC

DLL

Pclk

Synclk

Gear

Ratio

Logic

Figure 3. DDLL Including Details of DRCG

Phase Detector Signals

The DRCG Phase Detector (ÏD) receives two inputs from the

core logic, PCLKM (Pclk/M) and SYNCLKN (Synclk/N). The M

and N dividers in the core logic are chosen so that the frequen-

cies of PCLKM and SYNCLKN are identical. The Phase De-

tector (ÏD) detects the phase difference between the two input

clocks, and drives the DRCG Phase Aligner to null the input

phase error through the distributed loop. When the loop is

locked, the input phase error between PCLKM and SYNCLKN

is within the specification tERR,PD given in Table 13 after the

lock time given in the State Transition Section.

The Phase Detector (ÏD) aligns the rising edge of PCLKM to

the rising edge of SYNCLKN. The duty cycle of the phase de-

tector input clocks will be within the specification DCIN,PD given

in Table 12. Because the duty cycles of the two phase detector

input clocks will not necessarily be identical, the falling edges

of PCLKM and SYNCLKN may not be aligned when the rising

edges are aligned.

The voltage levels of the PCLKM and SYNCLKN signals are

determined by the controller. The pin VDDIPD is used as the

voltage reference for the phase detector inputs and should be

connected to the output voltage supply of the controller. In

some applications, the DRCG PLL output clock will be used

directly, by bypassing the Phase Aligner. If PCLKM and SYN-

CLKN are not used, those inputs must be grounded.

Selection Logic

Table 1 shows the logic for selecting the PLL prescaler and

feedback dividers to determine the multiply ratio for the PLL

from the input Refclk. Divider A sets the feedback and divider

B sets the prescaler, so the PLL output clock frequency is set

by: PLLClk=Refclk*A/B.

Table 1. PLL Divider Selection

MULT0 MULT1 MULT2

TBD

Table 2 shows the logic for enabling the clock outputs, using

the STOP# input signal. When STOP# is HIGH, the DRCG is

in its normal mode, and CLK and CLK# are complementary

outputs following the Phase Aligner output (PAclk). When

STOP# is LOW, the DRCG is in the Clk Stop mode, the output

clock drivers are disabled (set to Hi-Z), and the CLK and CLK#

settle to the DC voltage VX,STOP as given in Table 13. The level

of VX,STOP is set by an external resistor network.

Table 2. Clk Stop Mode Selection

Mode

STOP#

CLK

CLK#

Normal

Clk Stop

PACLK

VX,STOP

PACLK#

VX,STOP

Table 3 shows the logic for selecting the Bypass and Test

modes. The select bits, S0, S1, and S2 control the selection of

these modes. The Bypass mode brings out the full-speed PLL

output clock, bypassing the Phase Aligner. The Test mode

brings the REFCLK input all the way to the output, bypassing

both the PLL and the Phase Aligner. In the Output Test mode

(OE), both the CLK and CLK# outputs are put into a high-

impedance state (Hi-Z). This can be used for component test-

ing and for board-level testing.

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