W234 Datasheet, PDF (7/12 Pages) Cypress Semiconductor – Dual Direct Rambus Clock Generator

W234
Table 7. State Transition Latency Specifications
Transition
A
From
Power-Down
To
Normal
C
Power-Down
Clk Stop
K
Power-Down
Test
G
VDD ON
Normal
H
VDD ON
Clk Stop
M
VDD ON
Test
J
Normal
Normal
E
Clk Stop
Normal
E
Clk Stop
Normal
F
Normal
Clk Stop
L
Test
Normal
N
Normal
Test
B,D
Normal or Clk Stop PWR_DWN#
Transition Latency
Symbol
Max.
Description
t_POWERUP
t_POWERUP
3 ms
3 ms
Time from PWR_DWN# to rising edge
CLK/CLK# output settled (excluding t_DIS-
TLOCK⁾
Time from PWR_DWN# rising edge until the
internal PLL and clock has turned ON and set-
tled.
t_POWERUP
t_POWERUP
t_POWERUP
3 ms
3 ms
3 ms
Time from PWR_DWN# rising edge to
CLK/CLK# output settled (excluding t_DIS-
TLOCK^).
Time from VDD is applied and settled until
CLK/CLK# output settled (excluding t_DIS-
TLOCK^).
Time from VDD is applied and settled until
internal PLL and clock has turned ON and
settled.
t_POWERUP
3 ms
Time from VDD is applied and settled until
internal PLL and clock has turned ON and
settled.
t_MULT
t_CLKON
1 ms
10 ns
Time from when MULT0, MULT1, or MULT2
changed until CLK/CLK# output resettled (ex-
cluding t_DISTLOCK).
Time from STOP# rising edge until CLK/CLK#
provides glitch-free clock edges.
t_CLKSETL
20 cycles Time from STOP# rising edge to CLK/CLK#
output settled to within 50 ps of the phase be-
fore CLK/CLK# was disabled.
t_CLKOFF
5 ns Time from STOP# falling edge to CLK/CLK#
output disabled.
t_CTL
t_CTL
t_POWERDN
3 ms
3 ms
1 ms
Time from when S0, S1, or S2 is changed until
CLK/CLK# output has resettled (excluding
t_DISTLOCK).
Time from when S0, S1, or S2 is changed until
CLK/CLK# output has resettled (excluding
t_DISTLOCK).
Time from PWR_DWN# falling edge to the de-
vice in PWR_DWN#.
Figure 5 shows that the CLK Stop to Normal transition goes
through three phases. During t_CLKON, the clock output is not
specified and can have glitches. For t_CLKON<t<t_CLKSETL, the
clock output is enabled and must be glitch-free. For
t>t_CLKSETL, the clock output phase must be settled to within
50 ps of the phase before the clock output was disabled. At this
time, the clock output must also meet the voltage and timing
specifications of Table 13. The outputs are in a high-imped-
ance state during the Clk Stop mode.
Table 8. Distributed Loop Lock Time Specification
Symbol Min.
Max.
Unit
Description
t_DISTLOCK
5
ms Time from when CLK/CLK# output is settled to when the phase error between
SYNCLKN and PCLKM falls within the t_ERR,PD spec in Table 13.
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