W234 Datasheet, PDF (6/12 Pages) Cypress Semiconductor – Dual Direct Rambus Clock Generator

W234
In Clk Stop mode, the clock source is on, but the output is
disabled (STOP# asserted). The VDDIPD reference input may
remain on or may be grounded during the Clk Stop mode. The
VDDIR reference input must remain on during the Clk Stop
mode.
In Normal mode, the clock source is on, and the output is en-
abled.
Table 6 lists the control signals for each state.
Table 6. Control Signals for Clock Source States
State
Clock Output
PWR_DWN# STOP# Source Buffer
Power-Down
0
X
OFF Ground
Clk Stop
1
0
ON Disabled
Normal
1
1
ON Enabled
Timing Diagrams
Figure 5 shows the timing diagrams for the various transitions
between states, and Table 7 specifies the latencies of each
state transition. Note that these transition latencies assume
the following:
• REFCLK input has settled and meets specification
shown in Table 12.
• MULT0, MULT1, MULT2, S0, S1, and S2 control signals
are stable.
Power-Down Exit and Entry
PWR_DWN#
t_POWERUP
CLK0/CLK0#
CLK1/CLK1#
Output Enable Control
t_ON
STOP#
t_CLKON
CLK0/CLK0#
CLK1/CLK1#
t_CLKSETL
t_POWERDN
t_STOP
t_CLKOFF
output clock clock enabled
not specified and glitch free
glitches may
occur.
clock output settled within
50 ps of the phase before
disabled
Figure 5. State Transition Timing Diagrams
MULT0 and/or MULT1 and/or MULT2
CLK0/CLK0#
CLK1/CLK1#
t_MULT
Figure 6. Multiply Transition Timing
6