PAL20V8 Datasheet, PDF (9/13 Pages) Cypress Semiconductor – Flash Erasable, Reprogrammable CMOS PAL Device

PALCE20V8
Functional Logic Diagram for PALCE20V8
PIN NUMBERS DIP(PLCC) PACKAGE
1 (2)
2 (3)
PIN NUMBERS DIP(PLCC)PACKAGE
0
4
8
12 16 20 24 28 32 32 PTD
1
0
CG₀
0
280
3 (4)
MC7
CL1=2560
CL0=2632
320
600
4 (5)
MC6
CL1=2561
CL0=2633
640
920
5 (6)
MC5
CL1=2562
CL0=2634
960
1240
6 (7)
MC4
CL1=2563
CL0=2635
1280
1560
7 (9)
MC3
CL1=2564
CL0=2636
1600
1880
8 (10)
MC2
CL1=2565
CL0=2637
1920
2200
9 (11)
MC1
CL1=2566
CL0=2638
2240
2520
10 (12)
11 (13)
ELECTRONIC SIGNATURE ROW
2568 2569 . . .
. . . 2630
2631
BYTE7 BYTE6 . . .
. . . BYTE1 BYTE0
MSB LSB
MC0
CL1=2567
CL0=2639
0
1
CG₀
CG₀=2704
CG1=2705
23 (27)
22 (26)
21 (25)
20 (24)
19 (23)
18 (21)
17 (20)
16 (19)
15 (18)
14 (17)
13 (16)
20V8–9
9