PAL20V8 Datasheet, PDF (6/13 Pages) Cypress Semiconductor – Flash Erasable, Reprogrammable CMOS PAL Device

PALCE20V8
Commercial and Industrial Switching Characteristics^[2]
20V8−5
20V8−7
20V8−10
20V8−15
20V8−25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t_PD
Input to Output
Propagation Delay^[8]
1
5
1 7.5 1 10 1 15 1 25 ns
t_PZX
OE to Output Enable
t_PXZ
OE to Output Disable
t_EA
Input to Output
Enable Delay^[7]
5
6
10
15
20 ns
5
6
10
15
20 ns
6
9
10
15
25 ns
t_ER
Input to Output
Disable Delay^[7,9]
6
9
10
15
25 ns
t_CO
Clock to Output Delay^[8]
1
4
1
5
1
7
1 10 1 12 ns
t_S
Input or Feedback
Set-Up Time
3
7
10
12
15
ns
t_H
Input Hold Time
0
0
0
0
0
ns
t_P
External Clock Period
7
(t_CO + t_S)
t_WH
Clock Width HIGH^[7]
3
t_WL
Clock Width LOW^[7]
3
12
17
22
27
ns
5
8
8
12
ns
5
8
8
12
ns
f_MAX1
External Maximum
143
Frequency (1/(t_CO + t_S))^[7,10]
83
58
45.5
37
MHz
f_MAX2
Data Path Maximum
166.
100
62.5
62.5
41.6
MHz
Frequency
6
(1/(t_WH + t_WL))^{[7, 11]}
f_MAX3
Internal Feedback Maximum 166.
Frequency (1/(t_CF + t_S))^[7,12]
6
100
62.5
50
40
MHz
t_CF
Register Clock to
Feedback Input^{[7, 13]}
3
3
6
8
10 ns
t_PR
Power-Up Reset Time^[7]
1
1
1
1
1
µs
Shaded area contains preliminary information.
Notes:
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous
HIGH level has fallen to 0.5 volts below V_OH min. or a previous LOW level has risen to 0.5 volts above V_OL max.
10. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
11. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
13. This parameter is calculated from the clock period at f_MAX internal (1/f_MAX3) as measured (see Note 7 above) minus t_S.
6