PAL20V8 Datasheet, PDF (2/13 Pages) Cypress Semiconductor – Flash Erasable, Reprogrammable CMOS PAL Device

PALCE20V8
Pin Configuration
DIP/QSOP
Top View
CLK/I₀ 1
I₁ 2
I₂ 3
I₃ 4
I₄ 5
I_{5 6}
I_{6 7}
I₇ 8
I₈ 9
I₉ 10
I₁₀ 11
GND ¹²
24 V_CC
23 I13
22 I/O₇
21 I/O6
20 I/O₅
19 I/O4
18 I/O3
17 I/O2
16 ^I/O1
15 I/O0
14 I₁₂
13 OE/I₁₁
20V8–2
PLCC/LCC
Top View
4 3 2 1 2827 26
I₃ 5
25 I/O6
I₄ 6
24 I/O5
I_{5 7}
23 I/O4
NC 8
22 NC
I₆ 9
21 I/O3
I₇ 10
20 I/O2
I₈
11
121314
1516 1718 ¹⁹
I/O₁
20V8–3
Selection Guide
Generic Part Number
t_PD ns
Com’l/Ind Mil
PALCE20V8−5
5
PALCE20V8−7
7.5
PALCE20V8−10
10
10
PALCE20V8−15
15
15
PALCE20V8−25
25
25
PALCE20V8L−15
15
15
PALCE20V8L−25
25
25
Shaded area contains preliminary information.
t_S ns
Com’l/Ind Mil
3
7
10
10
12
12
15
20
12
12
15
20
t_CO ns
Com’l/Ind Mil
4
5
7
10
10
12
12
20
10
12
12
20
I_CC mA
Com’l Mil/Ind
115
115
115
130
90
130
90
130
55
65
55
65
Functional Description (continued)
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
Power-Up Reset
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Input and I/O Pin Pull-Ups
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, V_CC, or
Ground to improve noise immunity and reduce I_CC.
2