PAL20V8 Datasheet, PDF (7/13 Pages) Cypress Semiconductor – Flash Erasable, Reprogrammable CMOS PAL Device

PALCE20V8
Military Switching Characteristics^[2]
Parameter
Description
t_PD
Input to Output
Propagation Delay^[8]
t_PZX
t_PXZ
t_EA
t_ER
t_CO
t_S
t_H
t_P
t_WH
t_WL
f_MAX1
f_MAX2
f_MAX3
t_CF
t_PR
OE to Output Enable
OE to Output Disable
Input to Output Enable Delay^[7]
Input to Output Disable Delay^[7,9]
Clock to Output Delay^[8]
Input or Feedback Set-Up Time
Input Hold Time
External Clock Period (t_CO + t_S)
Clock Width HIGH^[7]
Clock Width LOW^[7]
External Maximum Frequency
(1/(t_CO + t_S)^[7,10]
Data Path Maximum Frequency
(1/(t_WH + t_WL))^{[7, 11 ]}
Internal Feedback Maximum
Frequency (1/(t_CF + t_S))^[7,12]
Register Clock to
Feedback Input^{[7, 13]}
Power-Up Reset Time^[7]
Shaded area contains preliminary information.
20V8−10
Min. Max.
1
10
20V8−15
Min. Max.
1
15
20V8−25
Min. Max.
1
25
Unit
ns
10
15
20
ns
10
15
20
ns
10
15
25
ns
10
15
25
ns
1
10
1
12
1
20
ns
10
12
20
ns
0
0
0
ns
20
24
40
ns
8
10
15
ns
8
10
15
ns
50
41.7
25
MHz
62.5
50
33.3
MHz
62.5
50
33.3
MHz
6
8
10
ns
1
1
1
µs
7