CY8C58LP Datasheet, PDF (9/122 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 5LP: CY8C58LP Family
PRELIMINARY
Datasheet
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
VSSA
VDDD
VSSD
VDDA
VSSD
Plane
VSSA
P la n e
3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for
high-current DACs (IDAC).
Opamp0out, Opamp1out, Opamp2out, Opamp3out. High
current output of uncommitted opamp.^[7]
Extref0, Extref1. External reference input to the analog system.
SAR0 EXTREF, SAR1 EXTREF. External references for SAR
ADCs
Opamp0-, Opamp1-, Opamp2-, Opamp3-. Inverting input to
uncommitted opamp.
Opamp0+, Opamp1+, Opamp2+, Opamp3+. Noninverting
input to uncommitted opamp.
GPIO. Provides interfaces to the CPU, digital peripherals,
analog peripherals, interrupts, LCD segment drive, and
CapSense.^[7]
I2C0: SCL, I2C1: SCL. I²C SCL line providing wake from sleep
on an address match. Any I/O pin can be used for I²C SCL if
wake from sleep is not required.
I2C0: SDA, I2C1: SDA. I²C SDA line providing wake from sleep
on an address match. Any I/O pin can be used for I²C SDA if
wake from sleep is not required.
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25-MHz crystal oscillator
pin.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
Notes
7. GPIOs with opamp outputs are not recommended for use with CapSense.
SIO. Provides interfaces to the CPU, digital peripherals and
interrupts with a programmable high threshold voltage, analog
comparator, high sink current, and high impedance state when
the device is unpowered.
SWDCK. SWD Clock programming and debug port connection.
SWDIO. SWD Input and Output programming and debug port
connection.
TCK. JTAG Test Clock programming and debug port connection.
TDI. JTAG Test Data In programming and debug port
connection.
TDO. JTAG Test Data Out programming and debug port
connection.
TMS. JTAG Test Mode Select programming and debug port
connection.
TRACECLK. Cortex-M3 TRACEPORT connection, clocks
TRACEDATA pins.
TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections,
output data.
SWV. SWV output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from VDDD instead
of from a VDDIO. Pins are Do Not Use (DNU) on devices without
USB.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from VDDD instead
of from a VDDIO. Pins are Do Not Use (DNU) on devices without
USB.
VBOOST. Power sense connection to boost pump.
Document Number: 001-84932 Rev. **
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