CY8C58LP Datasheet, PDF (86/122 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 5LP: CY8C58LP Family
PRELIMINARY
Datasheet
Figure 11-37. SAR ADC I_DD vs sps, V_DDA = 5 V, Continuous
Sample Mode, External Reference Mode
Table 11-29. SAR ADC AC Specifications^[48]
Parameter
Fclk
Tc
Description
SAR clock frequency
Conversion time
SINAD
THD
Startup time
Signal-to-noise ratio
Total harmonic distortion
Conditions
Min Typ
Max
1
–
18
One conversion requires 18 SAR
1
–
18
clocks. Maximum sample rate is 1
Msps
–
–
10
68
–
–
–
–
0.02
Units
MHz
µs
µs
dB
%
Figure 11-38. SAR ADC Noise Histogram, 1000 samples,
700 ksps, Internal Reference No Bypass, V_IN = VREF/2
Figure 11-39. SAR ADC Noise Histogram, 1000
samples, 700 ksps, Internal Reference Bypassed, V_IN =
VREF/2
Note
47. Based on device characterization (Not production tested).
Document Number: 001-84932 Rev. **
Page 86 of 122