CY8C58LP Datasheet, PDF (28/122 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 5LP: CY8C58LP Family
PRELIMINARY
Datasheet
The switching frequency is set to 400 kHz using an oscillator in
the boost converter block. The VBOOST is limited to 4 × VBAT.
The boost converter can be operated in two different modes:
active and sleep. Active mode is the normal mode of operation
where the boost regulator actively generates a regulated output
voltage.
The boost typically draws 250 µA in active mode and 25 µA in
sleep mode. The boost operating modes must be used in
conjunction with chip power modes to minimize total power
consumption. Table 6-4 lists the boost power modes available in
different chip power modes.
Table 6-4. Chip and Boost Power Modes Compatibility
Chip Power Modes
Chip -Active or
alternate active mode
Chip -Sleep mode
Chip-Hibernate mode
Boost Power Modes
Boost must be operated in its active
mode.
Boost can be operated in either active
or sleep mode. In boost sleep mode,
the chip must wake up periodically for
boost active-mode refresh.
Boost can be operated in either active
or sleep mode. However, it is
recommended not to use the boost with
chip hibernate mode due to the higher
current consumption. In boost sleep
mode, the chip must wake up
periodically for boost active-mode
refresh.
If the boost converter is not used, tie the VBAT, VSSB, and
VBOOST pins to ground and leave the Ind pin unconnected.
6.3 Reset
CY8C58LP has multiple internal and external reset sources
available. The reset sources are:
■ Power source monitoring - The analog and digital power
voltages, VDDA, VDDD, VCCA, and VCCD are monitored in
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
■ External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must
all have voltage applied before the part comes out of reset.
■ Watchdog timer - A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
■ Software - The device can be reset under program control.
Figure 6-7. Resets
VDDD VDDA
Reset
Pin
Power
Voltage
Level
Monitors
External
Reset
Processor
Interrupt
Reset
Controller
System
Reset
Watchdog
Timer
Software
Reset
Register
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register shows some of the resets or power voltage
monitoring interrupts. The program may examine this register to
detect and report certain exception conditions. This register is
cleared after a power-on reset. For details see the Technical
Reference Manual.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
■ IPOR - Initial Power-on-Reset
At initial power on, IPOR monitors the power voltages V_DDD,
V_DDA, V_CCD and V_CCA. The trip level is not precise. It is set to
approximately 1 volt, which is below the lowest specified
operating voltage but high enough for the internal circuits to be
reset and to hold their reset state. The monitor generates a
reset pulse that is at least 150 ns wide. It may be much wider
if one or more of the voltages ramps up slowly.
If after the IPOR triggers either V_DDX drops back below the
trigger point, in a non-monotonic fashion, it must remain below
that point for at least 10 µs. The hysteresis of the IPOR trigger
point is typically 100 mV.
After boot, the IPOR circuit is disabled and voltage supervision
is handed off to the precise low-voltage reset (PRES) circuit.
■ PRES - Precise Low-Voltage Reset
This circuit monitors the outputs of the analog and digital
internal regulators after power up. The regulator outputs are
compared to a precise reference voltage. The response to a
PRES trip is identical to an IPOR reset.
In normal operating mode, the program cannot disable the
digital PRES circuit. The analog regulator can be disabled,
which also disables the analog portion of the PRES. The PRES
circuit is disabled automatically during sleep and hibernate
modes, with one exception: During sleep mode the regulators
are periodically activated (buzzed) to provide supervisory
Document Number: 001-84932 Rev. **
Page 28 of 122