CY8C20XX6A_13 Datasheet, PDF (9/51 Pages) Cypress Semiconductor – 1.8 V Programmable CapSense® Controller with SmartSense™ Auto-tuning 1–33 Buttons, 0–6 Sliders

CY8C20XX6A/S
Pinouts
The CY8C20XX6A/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables. Every
port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, V_SS, V_DD, and XRES are
not capable of Digital I/O.
16-pin QFN (10 Sensing Inputs)^{[3, 4]}
Table 1. Pin Definitions – CY8C20236A, CY8C20246A, CY8C20246AS PSoC Device
Pin
No.
Type
Digital Analog
Name
Description
1
I/O
I
P2[5] Crystal output (XOut)
2
I/O
I
P2[3] Crystal input (XIn)
3 IOHR
I
P1[7] I²C SCL, SPI SS
4 IOHR
I
P1[5] I²C SDA, SPI MISO
5 IOHR
I
P1[3] SPI CLK
6 IOHR
I
P1[1] ISSP CLK^[5], I²C SCL, SPI
MOSI
7
Power
8 IOHR
I
V_SS
P1[0]
Ground connection
ISSP DATA^[5], I²C SDA, SPI
CLK^[6]
9 IOHR
I
P1[2]
10 IOHR
I
P1[4] Optional external clock
(EXTCLK)
11
Input
XRES Active high external reset with
internal pull-down
12 IOH
I
P0[4]
13
Power
14 IOH
I
V_DD Supply voltage
P0[7]
15 IOH
I
P0[3] Integrating input
16 IOH
I
P0[1] Integrating input
Figure 2. CY8C20236A, CY8C20246A, CY8C20246AS
AI, XOut, P2[5]
AI , XIn, P2[3]
AI , I2 C SCL, SPI SS, P1[7]
AI , I2 C SDA, SPI MISO, P1[5]
1
12
2
3
(
QFN
Top View)
11
10
4
9
P0[4] , AI
XRES
P1[4] , EXTCLK, AI
P1[2] , AI
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
3. 13 GPIOs = 10 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.
4. No Center Pad.
5. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
6. Alternate SPI clock.
Document Number: 001-54459 Rev. *T
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