CY8C20XX6A_13 Datasheet, PDF (12/51 Pages) Cypress Semiconductor – 1.8 V Programmable CapSense® Controller with SmartSense™ Auto-tuning 1–33 Buttons, 0–6 Sliders

CY8C20XX6A/S
30-ball WLCSP (24 Sensing Inputs) ^[15]
Table 4. Pin Definitions – CY8C20766A, CY8C20746A 30-ball WLCSP
Pin
No.
Type
Digital Analog
Name
Description
A1 IOH
I
P0[2]
A2 IOH
I
P0[6]
A3
Power
A4 IOH
I
V_DD Supply voltage
P0[1] Integrating Input
A5 I/O
I
P2[7]
B1 I/O
I
P2[6]
B2 IOH
I
P0[0]
B3 IOH
I
P0[4]
B4 IOH
I
P0[3] Integrating Input
B5 I/O
I
P2[5] Crystal Output (Xout)
C1 I/O
I
P2[2]
C2 I/O
I
P2[4]
C3 IOH
I
P0[7]
C4 IOH
I
P0[5]
C5 I/O
I
P2[3] Crystal Input (Xin)
D1 I/O
I
P2[0]
D2 I/O
I
P3[0]
D3 I/O
I
P3[1]
D4 I/O
I
P3[3]
D5 I/O
I
P2[1]
E1
Input
XRES Active high external reset with
internal pull-down
E2 IOHR
I
P1[6]
E3 IOHR
I
P1[4] Optional external clock input
(EXT CLK)
E4 IOHR
I
P1[7] I²C SCL, SPI SS
E5 IOHR
I
P1[5] I²C SDA, SPI MISO
F1 IOHR
I
P1[2]
F2 IOHR
I
P1[0] ISSP DATA^[16], I²C SDA, SPI
CLK^[17]
F3
Power
F4 IOHR
I
V_SS Supply ground
P1[1] ISSP CLK^[16], I²C SCL, SPI
MOSI
F5 IOHR
I
P1[3] SPI CLK
Figure 5. CY8C20766A 30-ball WLCSP
Bottom View
54
3
2
1
A
B
C
D
E
F
Top View
1
2
3
4
5
A
B
C
D
E
F
Notes
15. 27 GPIOs = 24 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.
16. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
17. Alternate SPI clock.
Document Number: 001-54459 Rev. *T
Page 12 of 51