CY8C20XX6A_13 Datasheet, PDF (27/51 Pages) Cypress Semiconductor – 1.8 V Programmable CapSense® Controller with SmartSense™ Auto-tuning 1–33 Buttons, 0–6 Sliders

CY8C20XX6A/S
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 27. AC Chip-Level Specifications
Symbol
Description
Conditions
Min
F_IMO24
F_IMO12
F_IMO6
F_CPU
F_32K1
F_{32K_U}
DC_IMO
DC_ILO
SR_{POWER_UP}
t_XRST
t_XRST2
IMO frequency at 24 MHz Setting
–
IMO frequency at 12 MHz setting
–
IMO frequency at 6 MHz setting
–
CPU frequency
–
ILO frequency
–
ILO untrimmed frequency
–
Duty cycle of IMO
–
ILO duty cycle
–
Power supply slew rate
V_DD slew rate during power-up
External reset pulse width at power-up After supply voltage is valid
External reset pulse width after
power-up^[58]
Applies after part has booted
22.8
11.4
5.7
0.75
15
13
40
40
–
1
10
t_OS
t_{JIT_IMO[59]}
Startup time of ECO
N=32
–
–
6 MHz IMO cycle-to-cycle jitter (RMS) –
6 MHz IMO long term N (N = 32)
–
cycle-to-cycle jitter (RMS)
6 MHz IMO period jitter (RMS)
–
12 MHz IMO cycle-to-cycle jitter (RMS) –
12 MHz IMO long term N (N = 32)
–
cycle-to-cycle jitter (RMS)
12 MHz IMO period jitter (RMS)
–
24 MHz IMO cycle-to-cycle jitter (RMS) –
24 MHz IMO long term N (N = 32)
–
cycle-to-cycle jitter (RMS)
24 MHz IMO period jitter (RMS)
–
Typ Max Units
24 25.2 MHz
12 12.6 MHz
6.0
6.3 MHz
– 25.20 MHz
32
50
kHz
32
82
kHz
50
60
%
50
60
%
–
250 V/ms
–
–
ms
–
–
s
1
–
s
0.7
6.7
ns
4.3 29.3
ns
0.7
3.3
ns
0.5
5.2
ns
2.3
5.6
ns
0.4
2.6
ns
1.0
8.7
ns
1.4
6.0
ns
0.6
4.0
ns
Notes
58. The minimum required XRES pulse length is longer when programming the device (see Table 33 on page 30).
59. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-54459 Rev. *T
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