CY8C53 Datasheet, PDF (87/102 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC )

PRELIMINARY
PSoC^® 5: CY8C53 Family Datasheet
11.8.3 Interrupt Controller
Table 11-70. Interrupt Controller AC Specifications
Parameter
Description
Conditions
Min
Delay from interrupt signal input to ISR Includes worse case completion of –
code execution from main line code longest instruction DIV with 6
cycles
Delay from interrupt signal input to ISR Includes worse case completion of –
code execution from ISR code
longest instruction DIV with 6
cycles
Typ Max Units
–
20 Tcy CPU
–
20 Tcy CPU
11.8.4 JTAG Interface
Table 11-71. JTAG Interface AC Specifications^[40]
Parameter
Description
f_TCK
TCK frequency
T_TDI_setup
T_TDI_hold
T_TDO_valid
T_TDO_hold
TDI, TMS setup before TCK high
TDI, TMS hold after TCK high
TCK low to TDO valid
TDO hold after TCK high
TCK to device outputs valid
Conditions
3.3 V  V_DDD  5 V
1.71 V  V_DDD < 3.3 V
T = 1/f_TCK
T = 1/f_TCK
T = 1/f_TCK
Min
–
–
0
T/4
2T/5
T/4
–
Typ Max Units
–
14^[41] MHz
–
7^[41]
MHz
–
–
ns
–
–
–
–
–
–
–
TBD
ns
11.8.5 SWD Interface
Table 11-72. SWD Interface AC Specifications^[40]
Parameter
Description
Conditions
f_SWDCK
SWDCLK frequency
3.3 V  V_DDD  5 V
1.71 V  V_DDD < 3.3 V
1.71 V  V_DDD < 3.3 V, SWD over
USBIO pins
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK
T_SWDI_hold SWDIO input hold after SWDCK high T = 1/f_SWDCK
T_SWDO_valid SWDCK low to SWDIO output valid T = 1/f_SWDCK
T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK
Min
–
–
–
T/4
T/4
2T/5
T/4
Typ Max Units
–
14^[42] MHz
–
7^[42]
MHz
–
5.5^[42] MHz
–
–
–
–
–
–
–
–
11.8.6 TPIU Interface
Table 11-73. TPIU Interface AC Specifications^[40]
Parameter
Description
TRACEPORT (TRACECLK) frequency
SWV bit rate
Conditions
Min
Typ Max Units
–
–
33^[43] MHz
–
–
33^[43] Mbit
Notes
40. Based on device characterization (Not production tested).
41. f_TCK must also be no more than 1/3 CPU clock frequency.
42. f_SWDCK must also be no more than 1/3 CPU clock frequency.
43. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency. See “GPIO” on page 63.for AC Specifications.
Document Number: 001-55035 Rev. *G
Page 87 of 102
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