CY8C53 Datasheet, PDF (23/102 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC )

PRELIMINARY
PSoC^® 5: CY8C53 Family Datasheet
6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled V_DDA, V_DDD, and Vddiox, respectively. It also
includes two internal 1.8 V regulators that provide the digital (V_CCD) and analog (V_CCA) supplies for the internal core logic. The output
pins of the regulators (V_CCD and V_CCA) and the V_DDIO pins must have capacitors connected as shown in Figure 6-4. The two V_CCD
pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R capacitor. The power system
also contains a sleep regulator, an I²C regulator, and a hibernate regulator.
Figure 6-4. PSoC Power System
Vddio2
1 µF
Vddd
0.1 µF
0.1 µF
Vddio0
I/O Supply
I/O Supply
I2C
Regulator
Vddio0
0.1 µF
Digital
Domain
Vssd
Digital
Regulators
Sleep
Regulator
Analog
Regulator
Analog
Domain
Vdda
Vcca
Vssa
Vdda
0.1 µF
1 µF
.
I/O Supply
0.1 µF
Vddio1
0.1µF
Vddd
Hibernate
Regulator
I/O Supply
0.1 µF
Vddio3
Note The two V_CCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-5.
6.2.1 Power Modes
PSoC 5 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low power and portable devices.
PSoC 5 power modes, in order of decreasing power
consumption are:
 Active
 Alternate Active
 Sleep
 Hibernate
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins. Figure 6-5 illustrates the allowable transitions
between power modes.
Document Number: 001-55035 Rev. *G
Page 23 of 102
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