CY8C53 Datasheet, PDF (45/102 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC )

PRELIMINARY
PSoC^® 5: CY8C53 Family Datasheet
Figure 7-19. CAN Controller Block Diagram
TxMessage0
TxReq
TxAbort
TxInterrupt
Request
(if enabled)
Tx Buffer
Status
TxReq
Pending
TxMessage1
TxReq
TxAbort
TxMessage6
TxReq
TxAbort
TxMessage7
TxReq
TxAbort
Rx Buffer
Status
RxMessage
Available
RxInterrupt
Request
(if enabled)
RxMessage0
RxMessage1
RxMessage14
RxMessage15
RTR RxMessages
0-15
Acceptance Code 0
Acceptance Code 1
Acceptance Mask 0
Acceptance Mask 1
Acceptance Code 14
Acceptance Code 15
Acceptance Mask 14
Acceptance Mask 15
Priority
Arbiter
Bit Timing
Tx
Tx
CAN
Framer
CRC
Generator
Error Status
Error Active
Error Passive
Bus Off
Tx Error Counter
Rx Error Counter
RxMessage
Handler
Rx
CAN
Framer
CRC Check
ErrInterrupt
Request
(if enabled)
Error Detection
CRC
Form
ACK
Bit Stuffing
Bit Error
Overload
Arbitration
Rx
WakeUp
Request
7.6 USB
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0
transceiver supporting all four USB transfer types: control,
interrupt, bulk, and isochronous. The maximum data payload
size is 64 bytes for control, interrupt, and bulk endpoints and
1023 bytes for isochronous. PSoC Creator provides full
configuration support. USB interfaces to hosts through two
dedicated USBIO pins, which are detailed in the “I/O System and
Routing” section on page 28.
USB includes the following features:
 Eight unidirectional data endpoints
 One bidirectional control endpoint 0 (EP0)
 Shared 512-byte buffer for the eight data endpoints
 Dedicated 8-byte buffer for EP0
 Three memory modes
 Manual Memory Management with No DMA Access
 Manual Memory Management with Manual DMA Access
 Automatic Memory Management with Automatic DMA
Access
 Internal 3.3 V regulator for transceiver
 Internal 48 MHz oscillator that auto locks to USB bus clock,
requiring no external crystal for USB (USB equipped parts only)
 Interrupts on bus and each endpoint event, with device wakeup
 USB Reset, Suspend, and Resume operations
 Bus powered and self powered modes
Figure 7-20. USB
Arbiter
512 X 8
SRAM
SIE
(Serial Interface
Engine)
Interrupts
48 MHz
IMO
USB
I/O
External 22 
D+ _Resistors
D–
Document Number: 001-55035 Rev. *G
Page 45 of 102
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