CY7C67300 Datasheet, PDF (86/119 Pages) Cypress Semiconductor – EZ-Host Programmable Embedded USB Host/Peripheral Controller

CY7C67300
7.12.1 SPI Configuration Register [0xC0C8] [R/W]
Bit #
Field
Read/Write
Default
15
3Wire
Enable
R/W
1
14
13
12
Phase
Select
SCK Polarity
Select
R/W
R/W
R/W
0
0
0
11
10
Scale Select
R/W
R/W
0
0
9
8
Reserved
R/W
-
0
0
Bit #
7
6
5
4
3
2
1
0
Field
Master
Active
Enable
Master
Enable
SS
Enable
SS Delay Select
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
1
1
1
1
1
Figure 7-73. SPI Configuration Register
Register Description
The SPI Configuration Register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
3Wire Enable (Bit 15)
The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation.
1: MISO and MOSI data lines are tied together
0: Normal MISO and MOSI Full Duplex operation (not tied together)
Phase Select (Bit 14)
The Phase Select bit selects advanced or delayed SCK phase. This field only applies to master mode.
1: Advanced SCK phase
0: Delayed SCK phase
SCK Polarity Select (Bit 13)
This SCK Polarity Select bit selects the polarity of SCK.
1: Positive SCK polarity
0: Negative SCK polarity
Scale Select (Bits [12:9])
The Scale Select field provides control over the SCK frequency, based on 48 MHz. Refer to Table 7-13 for a definition of this field.
This field only applies to master mode.
Table 7-13. Scale Select Field Definition for SCK Frequency
Scale Select [12:9]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
SCK Frequency
12 MHz
8 MHz
6 MHz
4 MHz
3 MHz
2 MHz
1.5 MHz
1 MHz
750 KHz
500 KHz
375 KHz
250 KHz
375 KHz
Document #: 38-08015 Rev. *E
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