CY7C67300 Datasheet, PDF (31/119 Pages) Cypress Semiconductor – EZ-Host Programmable Embedded USB Host/Peripheral Controller

CY7C67300
0: Overflow did not occur
Carry Flag (Bit 1)
The Carry Flag bit indicates if an arithmetic operation resulted in a Carry for addition, or borrow for subtraction.
1: Carry/Borrow occurred
0: Carry/Borrow did not occur
Zero Flag (Bit 0)
The Zero Flag bit indicates if an instruction execution resulted in a ‘0’.
1: Zero occurred
0: Zero did not occur
7.1.2 Bank Register [0xC002] [R/W]
Bit #
15
14
13
12
11
10
9
8
Field
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
1
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Reserved
Read/Write
R/W
R/W
R/W
-
-
-
-
-
Default
0
0
0
X
X
X
X
X
Figure 7-3. Bank Register
Register Description
The Bank Register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers
R0–R15. A register address is automatically generated by:
1. Shifting the four LSBs of the register address left by 1.
2. ORing the four shifted bits of the register address with the twelve MSBs of the Bank Register.
3. Forcing the LSB to zero.
For example, if the Bank Register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 will be
read. Refer to Table 7-1 for details.
Table 7-1. Bank Register Example
Register
Bank
R14
RAM Location
Hex Value
0x0100
0x000E << 1 = 0x001C
0x011C
Binary Value
0000 0001 0000 0000
0000 0000 0001 1100
0000 0001 0001 1100
Address (Bits [15:4])
The Address field is used as a base address for all register addresses to start from.
Reserved
All reserved bits should be written as ‘0’.
7.1.3 Hardware Revision Register [0xC004] [R]
Bit #
15
14
13
12
11
10
9
8
Field
Revision...
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
...Revision
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
Figure 7-4. Revision Register
Document #: 38-08015 Rev. *E
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