CY7C67300 Datasheet, PDF (18/119 Pages) Cypress Semiconductor – EZ-Host Programmable Embedded USB Host/Peripheral Controller

CY7C67300
4.4 General Purpose I/O Interface (GPIO)
EZ-Host has up to 32 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall
number of available GPIOs.
4.4.1 GPIO Description
All Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48-MHZ clock cycles. GPIO pins are
latched directly into registers, a single flip-flop.
4.4.2 Unused Pin Descriptions
Unused USB pins should be three-stated with the D+ line pulled high through the internal pull-up resistor and the D- line pulled
low through the internal pull-down resistor.
Unused GPIO pins should be configured as outputs and driven low.
4.5 UART Interface
EZ-Host has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a
development port or for other interface requirements. The UART interface is exposed through GPIO pins.
4.5.1 UART Features
• Supports baud rates of 900 to 115.2K
• 8-N-1
4.5.2 UART Pins.
Table 4-7. UART Interface Pins
Pin Name
TX
RX
Pin Number
42
43
4.6 I²C EEPROM Interface
EZ-Host provides a master only I²C interface for external serial EEPROMs. The serial EEPROM can be used to store application
specific code and data. This I²C interface is only to be used for loading code out of EEPROM, it is not a general I²C interface.
The I²C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Please refer to the BIOS documentation
for additional details on this interface.
4.6.1 I²C EEPROM Features
• Supports EEPROMs up to 64KB (512K bit)
• Auto-detection of EEPROM size
4.6.2 I2C EEPROM Pins.
Table 4-8. I2C EEPROM Interface Pins
Pin Name
Pin Number
SMALL EEPROM
SCK
39
SDA
40
LARGE EEPROM
SCK
40
SDA
39
4.7 Serial Peripheral Interface
EZ-Host provides a SPI interface for added connectivity. EZ-Host may be configured as either an SPI master or SPI slave. The
SPI interface can be exposed through GPIO pins or the External Memory port.
Document #: 38-08015 Rev. *E
Page 18 of 119