CY7C67300 Datasheet, PDF (19/119 Pages) Cypress Semiconductor – EZ-Host Programmable Embedded USB Host/Peripheral Controller

CY7C67300
4.7.1 SPI Features
• Master or slave mode operation
• DMA block transfer and PIO byte transfer modes
• Full duplex or half duplex data communication
• 8-byte receive FIFO and 8-byte transmit FIFO
• Selectable master SPI clock rates from 250 KHz to 12 MHz
• Selectable master SPI clock phase and polarity
• Slave SPI signaling synchronization and filtering
• Slave SPI clock rates up to 2 MHz
• Maskable interrupts for block and byte transfer modes
• Individual bit transfer for non-byte aligned serial communication in PIO mode
• Programmable delay timing for the active/inactive master SPI clock
• Auto or manual control for master mode slave select signal
• Complete access to internal memory
4.7.2 SPI Pins
The SPI port has a few different pin location options as shown in Table 4-9. The port location is selectable via the GPIO Control
Register [0xC006].
Table 4-9. SPI Interface Pins
Pin Name
Default Location
nSSI
SCK
MOSI
MISO
Alternate Location
nSSI
SCK
MOSI
MISO
Pin Number
56 or 65
61
60
66
73
72
71
74
4.8 High-speed Serial Interface
EZ-Host provides an HSS interface. The HSS interface is a programmable serial connection with baud rate from 9600 baud to
2.0 Mbaud. The HSS interface supports both byte and block mode operations as well as hardware and software handshaking.
Complete control of EZ-Host can be accomplished through this interface via an extensible API and communication protocol. The
HSS interface can be exposed through GPIO pins or the External Memory port.
4.8.1 HSS Features
• 8 bits, no parity code
• Programmable baud rate from 9600 baud to 2 Mbaud
• Selectable 1- or 2-stop bit on transmit
• Programmable inter-character gap timing for Block Transmit
• 8-byte receive FIFO
• Glitch filter on receive
• Block mode transfer directly to/from EZ-Host internal memory (DMA transfer)
• Selectable CTS/RTS hardware signal handshake protocol
• Selectable XON/XOFF software handshake protocol
• Programmable Receive interrupt, Block Transfer Done interrupts
• Complete access to internal memory
Document #: 38-08015 Rev. *E
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