BCM43903KUBGT Datasheet, PDF (83/87 Pages) Cypress Semiconductor – WICED™ IEEE 802.11 b/g/n SoC with an Embedded Applications Processor

BCM43903 Preliminary Data Sheet
Sequencing of Reset and Regulator Control Signals
Control Signal Timing Diagrams
Figure 18: REG_ON = High, No HIB_REG_ON_OUT Connection to REG_ON
32.678 kHz
Sleep Clock
VBAT
VDDIO
REG_ON
HIB_REG_ON_IN
~ 2 Sleep Cycles
Figure 19: HIB_REG_ON_IN = High, HIB_REG_ON_OUT Connected to REG_ON
32.678 kHz
Sleep Clock
VBAT
VDDIO
HIB_REG_ON_IN
~ 2 Sleep Cycles
Broadcom^®
March 12, 2016 • 43903-DS102-R
BROADCOM CONFIDENTIAL
Page 82