W234_02 Datasheet, PDF (8/14 Pages) Cypress Semiconductor – Dual Direct Rambus™ Clock Generator

W234
Table 7. State Transition Latency Specifications
Transi-
tion
From
Transition Latency
To
Symbol
Max.
Description
A
Power-Down
Normal
t_POWERUP
3 ms Time from PWR_DWN# to rising edge CLK/CLK#
output settled (excluding t_DISTLOCK)
C
Power-Down
Clk Stop
t_POWERUP
3 ms Time from PWR_DWN# rising edge until the in-
ternal PLL and clock has turned ON and settled.
K
Power-Down
Test
t_POWERUP
3 ms Time from PWR_DWN# rising edge to CLK/CLK#
output settled (excluding t_DISTLOCK).
G
VDD ON
Normal
t_POWERUP
3 ms Time from VDD is applied and settled until
CLK/CLK# output settled (excluding t_DISTLOCK).
H
VDD ON
Clk Stop
t_POWERUP
3 ms Time from VDD is applied and settled until
internal PLL and clock has turned ON and settled.
M
VDD ON
Test
t_POWERUP
3 ms Time from VDD is applied and settled until
internal PLL and clock has turned ON and settled.
J
Normal
Normal
t_MULT
1 ms Time from when MULT0, MULT1, or MULT2
changed until CLK/CLK# output resettled (ex-
cluding t_DISTLOCK).
E
Clk Stop
Normal
t_CLKON
10 ns Time from STOP# rising edge until CLK/CLK#
provides glitch-free clock edges.
E
Clk Stop
Normal
t_CLKSETL 20 cycles Time from STOP# rising edge to CLK/CLK# out-
put settled to within 50 ps of the phase before
CLK/CLK# was disabled.
F
Normal
Clk Stop
t_CLKOFF
5 ns Time from STOP# falling edge to CLK/CLK# out-
put disabled.
L
Test
Normal
t_CTL
N
Normal
Test
t_CTL
B,D
Normal or Clk Stop PWR_DWN t_POWERDN
#
3 ms
3 ms
1 ms
Time from when S0, S1, or S2 is changed until
CLK/CLK# output has resettled (excluding
t_DISTLOCK).
Time from when S0, S1, or S2 is changed until
CLK/CLK# output has resettled (excluding
t_DISTLOCK).
Time from PWR_DWN# falling edge to the device
in PWR_DWN#.
Figure 5 shows that the CLK Stop to Normal transition goes
through three phases. During t_CLKON, the clock output is not
specified and can have glitches. For t_CLKON<t<t_CLKSETL, the
clock output is enabled and must be glitch-free. For
t>t_CLKSETL, the clock output phase must be settled to within
50 ps of the phase before the clock output was disabled. At
this time, the clock output must also meet the voltage and tim-
ing specifications of Table 13. The outputs are in a high-imped-
ance state during the Clk Stop mode.
Table 8. Distributed Loop Lock Time Specification
Symbol Min.
Max.
Unit
Description
t_DISTLOCK
5
ms Time from when CLK/CLK# output is settled to when the phase error between
SYNCLKN and PCLKM falls within the t_ERR,PD spec in Table 13.
Document #: 38-07232 Rev. *B
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