W234_02 Datasheet, PDF (7/14 Pages) Cypress Semiconductor – Dual Direct Rambus™ Clock Generator

Timing Diagrams
Power-Down Exit and Entry
PWR_DWN#
t_POWERUP
CLK0/CLK0#
CLK1/CLK1#
Output Enable Control
t_ON
STOP#
CLK0/CLK0#
CLK1/CLK1#
t_CLKON
t_CLKSETL
t_POWERDN
t_STOP
t_CLKOFF
output clock clock enabled
not specified and glitch free
glitches may
occur.
clock output settled within
50 ps of the phase before
disabled
Figure 5. State Transition Timing Diagrams.
MULT0 and/or MULT1 and/or MULT2
CLK0/CLK0#
CLK1/CLK1#
t_MULT
Figure 6. Multiply Transition Timing.
W234
Document #: 38-07232 Rev. *B
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