W234_02 Datasheet, PDF (6/14 Pages) Cypress Semiconductor – Dual Direct Rambus™ Clock Generator

W234
V_{DD MTurn-On}
V_DD
Turn-On
G
L
Test
N
J
Normal
B
K
A
F
E
V_DD Turn-On
D
Power-Down
C
Clk Stop
V_DD Turn-On
H
Figure 4. Clock Source State Diagram.
In Clk Stop mode, the clock source is on, but the output is
disabled (STOP# asserted). The VDDIPD reference input may
remain on or may be grounded during the Clk Stop mode. The
VDDIR reference input must remain on during the Clk Stop
mode.
In Normal mode, the clock source is on, and the output is en-
abled.
Table 6 lists the control signals for each state.
Table 6. Control Signals for Clock Source States
State
Clock Output
PWR_DWN# STOP# Source Buffer
Power-Down
0
X
OFF Ground
Clk Stop
1
0
ON Disabled
Normal
1
1
ON Enabled
Figure 5 shows the timing diagrams for the various transitions
between states, and Table 7 specifies the latencies of each
state transition. Note that these transition latencies assume
the following:
• REFCLK input has settled and meets specification shown
in Table 12.
• MULT0, MULT1, MULT2, S0, S1, and S2 control signals
are stable.
Document #: 38-07232 Rev. *B
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