W234_02 Datasheet, PDF (10/14 Pages) Cypress Semiconductor – Dual Direct Rambus™ Clock Generator

W234
Table 12. Operating Conditions^[2]
Parameter
Description
Min.
Max.
Unit
V_DD
T_A
t_CYCLE,IN
t_J,IN
DC_IN
FM_IN
PM_IN[4]
Supply Voltage
Ambient Operating Temperature
Refclk Input Cycle Time
Input Cycle-to-Cycle Jitter^[3]
Input Duty Cycle over 10,000 Cycles
Input Frequency of Modulation
Modulation Index for Triangular Modulation
Modulation Index for Non-Triangular Modulation
3.135
0
10
–
40
30
–
–
3.465
70
40
250
60
33
0.6
0.5^[5]
V
°C
ns
ps
%t_CYCLE
kHz
%
%
t_CYCLE,PD
t_ERR,INIT
DC_IN,PD
t_I,SR
C_IN,PD
∆C_IN,PD
C_IN,CMOS
Phase Detector Input Cycle Time at PCLKM & SYNCLKN
Initial Phase error at Phase Detector Inputs
Phase Detector Input Duty Cycle over 10,000 Cycles
Input Slew Rate (measured at 20%-80% of input voltage) for
PCLKM, SYNCLKN, and REFCLK
Input Capacitance at PCLKM, SYNCLKN, and REFCLK^[6]
Input Capacitance matching at PCLKM and SYNCLKN^[6]
Input Capacitance at CMOS pins (excluding PCLKM, SYNCLKN,
and REFCLK)^[6]
30
–0.5
25
1
–
–
–
100
ns
0.5
t_CYCLE,PD
75
t_CYCLE,PD
4
V/ns
7
pF
0.5
pF
10
pF
V_IL
Input (CMOS) Signal Low Voltage
–
0.3
VDD
V_IH
Input (CMOS) Signal High Voltage
0.7
-
VDD
V_IL,R
Refclk Input Low Voltage
-
0.3
V_DDIR
V_IH,R
Refclk Input High Voltage
0.7
–
V_DDIR
V_IL,PD
Input Signal Low Voltage for PD Inputs and STOP#
–
0.3
V_DDIPD
V_IH,PD
Input Signal High Voltage for PD Inputs and STOP#
0.7
–
V_DDIPD
V_DDIR
Input Supply Reference for REFCLK
1.235
3.465
V
V_DDIPD
Input Supply Reference for PD Inputs
1.235
2.625
V
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Refclk jitter measured at V_DDIR (nom)/2.
4. If input modulation is used: input modulation is allowed but not required.
5. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
6. Capacitance measured at Freq = 1 MHz, DC bias = 0.9V and V_AC < 100 mV.
Document #: 38-07232 Rev. *B
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