W147G Datasheet, PDF (8/12 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic

PRELIMINARY
W147G
W147G Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be writ-
ten to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current.
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
4. Only Byte 0, 1 and 2 are defined in W147G Byte 3 to Byte
7 are reserved and must be written to “zero.”
Byte 0: Control Register (1 = Enable, 0= Disable)^[14]
Bit
Pin#
Name
Pin Description
Bit 7
-
Reserved
(Active/Inactive)
Bit 6
-
Reserved
(Active/Inactive)
Bit 5
-
Reserved
(Active/Inactive)
Bit 4
-
Reserved
(Active/Inactive)
Bit 3
-
Spread Spectrum (1=On/0=Off)
(Active/Inactive)
Bit 2
26
DOT
(Active/Inactive)
Bit 1
25
USB
(Active/Inactive)
Bit 0
49
CPU2_ITP
(Active/Inactive)
Byte 1: Control Register (1 = Enable, 0= Disable)^[14]
Bit
Pin#
Name
Bit 7
36
SDRAM7
Bit 6
37
SDRAM6
Bit 5
39
SDRAM5
Bit 4
40
SDRAM4
Bit 3
42
SDRAM3
Bit 2
43
SDRAM2
Bit 1
45
SDRAM1
Bit 0
46
SDRAM0
Pin Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0= Disable)^[14]
Bit
Pin#
Name
Pin Description
Bit 7
20
PCI7
(Active/Inactive)
Bit 6
19
PCI6
(Active/Inactive)
Bit 5
18
PCI5
(Active/Inactive)
Bit 4
16
PCI4
(Active/Inactive)
Bit 3
15
PCI3
(Active/Inactive)
Bit 2
13
PCI2
(Active/Inactive)
Bit 1
12
PCI1
(Active/Inactive)
Bit 0
-
Reserved
(Active/Inactive)
Note:
14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
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