W147G Datasheet, PDF (2/12 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic

PRELIMINARY
W147G
Pin Definitions
Pin Name
REF/APICDIV
Pin No.
1
X1
X2
PCI0_ICH,
PCI1:7
3V66_0:1
USB
DOT
SEL0:1
PWRDWN#
CPU2_ITP,
CPU0:1
SDRAM0:7,
DCLK
APIC0:1
3
4
11, 12, 13, 15,
16, 18, 19. 20
7, 8
25
26
28, 29
32
49, 52, 50
46, 45, 43, 42,
40, 39, 37, 36,
34
55, 54
SDATA
SCLK
VDDQ3
VDD3
VDDQ2
GND
30
31
2, 9, 10, 21, 27,
33, 38, 44
22
51, 53
5, 6, 14, 17, 23,
24, 35, 41, 47,
48, 56
Pin
Type
I/O
I
I
O
O
O
O
I
I
O
O
Pin Description
Reference Clock: 3.3V 14.318-MHz clock output. This pin doubles as the select
strap for APIC clock frequency. If strapped LOW during power up, APIC clock runs
at half PCI clock speed. Otherwise, APIC clocks run at PCI clock speed.
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection as an external reference frequency input.
Crystal Output: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
PCI Clock 0 through 7: 3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually
turned off via I²C interface.
66-MHz Clock Output: 3.3V fixed 66-MHz clock.
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock outputs.
Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal.
Clock Function Selection pins: LVTTL-compatible input to select device func-
tions. See Table 1 for detailed descriptions.
Power Down Control: LVTTL-compatible asynchronous input that places the de-
vice in power-down mode when held LOW.
CPU Clock Outputs: Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz or 100 MHz depending on the configuration
of SEL0:1. Voltage swing set by V_DDQ2.
SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:7 can be
individually turned off via I²C interface.
O Sychronous APIC Clock Outputs: Clock outputs running divide synchronous
with the PCI clock outputs. Output frequency is controlled by the strap option on
REF. Voltage swing set by V_DDQ2.
I/O Data pin for I²C circuitry.
I Clock pin for I²C circuitry.
P 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
P 3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to
3.3V.
P 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
G Ground Connections: Connect all ground pins to the common system ground
plane.
2