W147G Datasheet, PDF (1/12 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic

PRELIMINARY
W147G
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Three copies of CPU clock at 66/100 MHz
• Nine copies of 100-MHz SDRAM clocks
• Eight copies of PCI clock
• Two copies of synchronous APIC clock
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
• Two copies of 66-MHz fixed clock
• One copy of 14.31818-MHz reference clock
• Power-down control
• I²C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
APIC, 48MHz, SDRAM Output Skew: ......................... 250 ps
CPU, 3V66 Output Skew: ............................................175 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Table 1. Pin Selectable Functions
SEL1
SEL0
0
0
0
1
1
0
1
1
Function
Three-state
Test
66-MHz CPU
100-MHz CPU
Block Diagram
X1
X2
SDATA
SCLK
SEL0:1
XTAL
OSC
PLL REF FREQ
I²C
Logic
D i vi d e r,
D el a y,
and
Phase
Control
Logic
PLL 1
PWRDWN#
VDDQ3
REF/APICDIV
VDDQ2
CPU0:1
2
CPU2_ITP
APIC0:1
2
VDDQ3
3V66_0:1
2
PCI0_ICH
PCI1:7
7
DCLK
SDRAM0:7
8
PLL2
VDDQ3
USB
DOT
Pin Configuration
REF/APICDIV 1
VDDQ3 2
X1 3
X2 4
GND 5
GND 6
3V66_0 7
3V66_1 8
VDDQ3 9
VDDQ3 10
PCI0_ICH 11
PCI1 12
PCI2 13
GND 14
PCI3 15
PCI4 16
GND 17
PCI5 18
PCI6 19
PCI7 20
VDDQ3 21
VDD3 22
GND 23
GND 24
USB 25
DOT 26
VDDQ3 27
SEL0 28
56 GND
55 APIC0
54 APIC1
53 VDDQ2
52 CPU0
51 VDDQ2
50 CPU1
49 CPU2_ITP
48 GND
47 GND
46 SDRAM0
45 SDRAM1
44 VDDQ3
43 SDRAM2
42 SDRAM3
41 GND
40 SDRAM4
39 SDRAM5
38 VDDQ3
37 SDRAM6
36 SDRAM7
35 GND
34 DCLK
33 VDDQ3
32 PWRDWN#
31 SCLK
30 SDATA
29 SEL1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **