W147G Datasheet, PDF (5/12 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic

PRELIMINARY
W147G
Power Down Control
W147G provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0ns
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
25ns
1
50ns
2
Figure 4. W147G PWRDWN# Timing Diagram^{[8, 9, 10, 11]}
75ns
Center
Table 3. W147G Maximum Allowed Current
W147
Condition
Powerdown Mode
(PWRDWN# = 0)
Max. 2.5V supply consumption
Max. discrete cap loads,
V_DDQ2 = 2.625V
All static inputs = V_DDQ3 or V_SS
100 µA
Max. 3.3V supply consumption
Max. discrete cap loads
V_DDQ3 = 3.465V
All static inputs = V_DDQ3 or V_SS
200 µA
Full Active 66 MHz
SEL1,0 = 10 (PWRDWN# =1)
70 mA
280 mA
Full Active 100 MHz
SEL1,0 =11 (PWRDWN# = 1)
100 mA
280 mA
Notes:
8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW
transition.
9. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W147G.
10. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.
11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
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