PALCE16V8 Datasheet, PDF (8/13 Pages) Advanced Micro Devices – EE CMOS 20-Pin Universal Programmable Array Logic

USE ULTRA37000™ FOR
ALL NEW DESIGNS
PALCE16V8
Functional Logic Diagram for PALCE16V8
PIN NUMBERS
INPUT LINE
PRODUCT LINE FIRST CELL NUMBERS
1
NUMBERS
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31
00
32
64
128 ⁹⁶
192 ¹⁶⁰
224
2
256
288
320
384 ³⁵²
448 ⁴¹⁶
480
3
512
544
576
640 ⁶⁰⁸
704 ⁶⁷²
736
4
768
800
832
896 ⁸⁶⁴
960 ⁹²⁸
992
5
1024
10881056
1120
1152
1184
1216
1248
6
1280
1312
1344
14081376
14721440
1504
7
1536
1568
1600
16641632
17281696
1760
8
1792
1824
1856
19201888
19841952
2016
9
PIN NUMBERS
V_CC
20
MC7
CL1=2048
CL0=2120
19
PTD=2128
-2135
MC6
CL1=2049
CL0=2121
18
PTD=2136
-2143
MC5
CL1=2050
CL0=2122
17
PTD=2144
-2151
MC4
CL1=2051
CL0=2123
16
PTD=2152
-2159
MC3
CL1=2052
CL0=2124
15
PTD=2160
-2167
MC2
CL1=2053
CL0=2125
14
PTD=2168
-2175
MC1
CL1=2054
CL0=2126
13
PTD=2176
-2183
MC0
CL1=2055
CL0=2127
12
PTD=2184
-2191
10
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31
11
USER ELECTRONIC SIGNATURE ROW
2056 2064 2072
2080
2088
2096
2104
2112 2119
GLOBAL ARCH BITS
BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7
CG₀=2192
CG₁=2193
MSB LSB
MSB LSB
Document #: 38-03025 Rev. *A
Page 8 of 13