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PALCE16V8 Datasheet, PDF (1/13 Pages) Advanced Micro Devices – EE CMOS 20-Pin Universal Programmable Array Logic
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PALCE16V8
Flash-Erasable Reprogrammable
CMOS PAL® Device
Features
• Up to 16 input terms and eight outputs
• Active pull-up on data input pins
• Low power version (16V8L)
— 55 mA max. commercial (10, 15, 25 ns)
— 65 mA max. industrial (10, 15, 25 ns)
— 65 mA military (15 and 25 ns)
• Standard version has low power
— 90 mA max. commercial (10, 15, 25 ns)
— 115 mA max. commercial (7 ns)
— 130 mA max. military/industrial (10, 15, 25 ns)
• CMOS Flash technology for electrical erasability and
reprogrammability
• PCI-compliant
• 7.5 ns com’l version
5 ns tCO
5 ns tS
7.5 ns tPD
125-MHz state machine
• 10 ns military/industrial versions
7 ns tCO
10 ns tS
10 ns tPD
62-MHz state machine
• High reliability
— Proven Flash technology
— 100% programming and functional testing
Functional Description
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combina-
torial operation
The Cypress PALCE16V8 is a CMOS Flash Electrical
Erasable second-generation programmable array logic
device. It is implemented with the familiar sum-of-product
(AND-OR) logic structure and the programmable macrocell.
Logic Block Diagram (PDIP/CDIP)
GND
I8
I7
I6
I5
I4
I3
I2
I1
CLK/I0
10
9
8
7
6
5
4
3
2
1
PROGRAMMABLE
AND ARRAY
(64 x 32)
8
8
8
8
8
8
8
8
Macrocell Macrocell Macrocell Macrocell
Macrocell Macrocell Macrocell Macrocell
11
12
OE/I9
I/O0
Pin Configurations
13
14
15
I/O1
I/O2
I/O3
DIP
Top View
16
17
18
19
20
I/O4
I/O5
I/O6
I/O7
VCC
PLCC/LCC
Top View
CLK/I0 1
I1 2
I2 3
I3 4
I4 5
I5 6
I6 7
I7 8
I8 9
GND 10
20 VCC
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 I/O2
13 I/O1
12 I/O0
11 OE/I9
3 2 1 2019
I3 4
18 I/O6
I4 5
17 I/O5
I5 6
16 I/O4
I6 7
15 I/O3
I7 8
14 I/O2
9 10111213
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03025 Rev. *A
Revised April 22, 2004
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