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CG5982AF Datasheet, PDF (7/12 Pages) Cypress Semiconductor – 2K x 8 Automotive Dual-port Static RAM
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESSL,R
ADDRESS MATCH
CEL
CER
BUSYR
CER Valid First:
ADDRESSL,R
tPS
tBLC
ADDRESS MATCH
tBHC
CER
CEL
BUSYL
tPS
tBLC
tBHC
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
ADDRESSL
ADDRESSR
BUSYR
Right Address Valid First:
ADDRESSR
ADDRESSL
BUSYL
tRC or tWC
ADDRESS MATCH
tPS
tBLA
tRC or tWC
ADDRESS MATCH
tPS
tBLA
ADDRESS MISMATCH
tBHA
ADDRESS MISMATCH
tBHA
CG5982AF
Document #: 38-06067 Rev. *C
Page 7 of 12
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