CG5982AF Datasheet, PDF (4/12 Pages) Cypress Semiconductor – 2K x 8 Automotive Dual-port Static RAM

CG5982AF
Switching Characteristics Over the Operating Range^{[4, 9]} (continued)
CG5982AF
Parameter
t_HZOE
t_HZCE
t_PU
t_PD
Write Cycle^[13]
Description
OE HIGH to High-Z^{[8, 11, 12]}
CE HIGH to High-Z^{[8, 11, 12]}
CE LOW to Power-Up^[8]
CE HIGH to Power-Down^[8]
Min. Max. Unit
25
ns
25
ns
0
ns
35
ns
t_WC
Write Cycle Time
t_SCE
CE LOW to Write End
t_AW
Address Set-up to Write End
t_HA
Address Hold from Write End
t_SA
Address Set-up to Write Start
t_PWE
R/W Pulse Width
t_SD
Data Set-up to Write End
t_HD
t_HZWE
t_LZWE
Data Hold from Write End
R/W LOW to High-Z ^[8]
R/W HIGH to Low-Z ^[8]
Busy/Interrupt Timing
55
ns
40
ns
40
ns
2
ns
0
ns
30
ns
20
ns
0
ns
25
ns
0
ns
t_BLA
t_BHA
t_BLC
t_BHC
t_PS
t_WB
t_WH
t_BDD
t_DDD
t_WDD
Interrupt Timing^[15]
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch^[14]
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH^[14]
Port Set-up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
30
ns
30
ns
30
ns
30
ns
5
ns
0
ns
35
ns
45
ns
Note 15 ns
Note 15 ns
t_WINS
R/W to INTERRUPT Set Time
45
ns
t_EINS
CE to INTERRUPT Set Time
45
ns
t_INS
t_OINR
t_EINR
t_INR
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time^[14]
CE to INTERRUPT Reset Time^[14]
Address to INTERRUPT Reset Time^[14]
45
ns
45
ns
45
ns
45
ns
Notes:
12. t_LZCE, t_LZWE, t_HZOE, t_LZOE, t_HZCE, and t_HZWE are tested with C_L = 5 pF, as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
13. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
14. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Document #: 38-06067 Rev. *C
Page 4 of 12
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