CG5982AF Datasheet, PDF (6/12 Pages) Cypress Semiconductor – 2K x 8 Automotive Dual-port Static RAM

Switching Waveforms (continued)
Write Cycle No.1 (OE Three-States Data I/Os—Either Port)^{[13, 19]}
ADDRESS
CE
R/W
t_WC
t_SCE
t_AW
t_SA
t_PWE
DATA_IN
t_SD
DATA VALID
t_HA
t_HD
CG5982AF
OE
D_OUT
t_HZOE
HIGH IMPEDANCE
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)^{[13, 20]}
t_WC
ADDRESS
t_SCE
t_HA
CE
R/W
t_AW
t_SA
t_PWE
DATA_IN
t_SD
t_HD
DATA VALID
D_OUT
t_HZWE
t_LZWE
HIGH IMPEDANCE
Notes:
19. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t_PWE or t_HZWE + t_SD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required t_SD.
20. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
Document #: 38-06067 Rev. *C
Page 6 of 12
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