CY8C3246LTI-149 Datasheet, PDF (68/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
11.2 Device Level Specifications
Specifications are valid for –40 °C  T_A  85 °C and T_J  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Parameter
V_DDA
V_DDA
Description
Conditions
Analog supply voltage and input to analog
core regulator
Analog core regulator enabled
Analog supply voltage, analog regulator
bypassed
Analog core regulator disabled
V_DDD
V_DDD
Digital supply voltage relative to V_SSD
Digital supply voltage, digital regulator
bypassed
Digital core regulator enabled
Digital core regulator disabled
V_DDIO^[19]
V_CCA
V_CCD
I/O supply voltage relative to V_SSIO
Direct analog core voltage input (Analog
regulator bypass)
Direct digital core voltage input (Digital
regulator bypass)
Analog core regulator disabled
Digital core regulator disabled
Min Typ^[22] Max
1.8 –
5.5
Units
V
1.71 1.8
1.8 –
–
–
1.71 1.8
1.71 –
–
–
1.71 1.8
1.89
V
V_DDA^[18]
V_DDA + 0.1^[24]
V
1.89
V
V_DDA^[18]
V
V_DDA + 0.1^[24]
1.89
V
1.71 1.8
1.89
V
Active Mode
Only IMO and CPU clock enabled. CPU
executing simple loop from instruction
buffer.
T = –40 °C –
V_DDX
F_CPU
=
=
2.7 V – 5.5
6 MHz^[23]
V;
T = 25 °C
T = 85 °C
–
–
1.2
1.2
4.9
2.9
3.1
7.7
T = –40 °C – 1.3
2.9
V_DDX
F_CPU
=
=
2.7 V – 5.5
3 MHz^[23]
V;
T = 25 °C
T = 85 °C
–
–
1.6
4.8
3.2
7.5
I_DD ^{[20, 21]}
T = –40 °C – 2.1
V_DDX = 2.7 V – 5.5 V;
F_CPU = 6 MHz
T = 25 °C
T = 85 °C
–
–
2.3
5.6
IMO enabled, bus clock and CPU clock
enabled. CPU executing program from
V_DDX
F_CPU
=
=
2.7
12
V – 5.5 V;
MHz^[23]
T = –40 °C
T = 25 °C
–
–
3.5
3.8
flash.
T = 85 °C – 7.1
3.7
3.9
8.5
5.2
mA
5.5
9.8
V_DDX
F_CPU
=
=
2.7
24
V – 5.5 V;
MHz^[23]
T = –40 °C
T = 25 °C
–
–
6.3
6.6
8.1
8.3
T = 85 °C –
10
13
V_DDX
F_CPU
=
=
2.7
48
V – 5.5 V;
MHz^[23]
T = –40 °C
T = 25 °C
–
–
11.5
12
13.5
14
T = 85 °C – 15.5
18.5
Notes
18. The power supplies can be brought up in any sequence however once stable V_DDA must be greater than or equal to all other supplies.
19. The V_DDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin V_DDIO  V_DDA.
20. Total current for all power domains: digital (I_DDD), analog (I_DDA), and I/Os (I_{DDIO0, 1, 2, 3}). Boost not included. All I/Os floating.
21. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
PSoC Creator, the integrated design environment. To estimate total current, find the CPU current at the frequency of interest and add peripheral currents for your
particular system from the device datasheet and component datasheets.
22. V_DDX = 3.3 V.
23. Based on device characterizations (Not production tested).
24. Guaranteed by design, not production tested.
Document Number: 001-56955 Rev. *Y
Page 68 of 128