CY8C3246LTI-149 Datasheet, PDF (102/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
Bus Clock
EM_Clock
EM_Addr
Figure 11-54. Synchronous Write and Read Cycle Timing, No Wait States
Tbus_clock
EM_CE
EM_ADSC
EM_WE
EM_OE
EM_Data
Twr_setup
Write Cycle
Minimum of 4 bus clock cycles between successive EMIF accesses
Trd_setup
Trd_hold
Read Cycle
Table 11-54. Synchronous Write and Read Timing Specifications^[59]
Parameter
Fbus_clock
Tbus_clock
Twr_Setup
Trd_setup
Trd_hold
Description
Bus clock frequency^[60]
Bus clock period^[61]
Time from EM_data valid to rising edge
of EM_Clock
Time that EM_data must be valid before
rising edge of EM_OE
Time that EM_data must be valid after
rising edge of EM_OE
Conditions
Min
Typ
–
–
30.3
–
Tbus_clock – 10
–
5
–
5
–
Max Units
33
MHz
–
ns
–
ns
–
ns
–
ns
Notes
59. Based on device characterization (Not production tested).
60. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 76.
61. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.
Document Number: 001-56955 Rev. *Y
Page 102 of 128