CY8C3246LTI-149 Datasheet, PDF (64/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
9.2 Serial Wire Debug Interface
The SWD interface is the preferred alternative to the JTAG
interface. It requires only two pins instead of the four or five
needed by JTAG. SWD provides all of the programming and
debugging features of JTAG at the same speed. SWD does not
provide access to scan chains or device chaining. The SWD
clock frequency can be up to 1/3 of the CPU clock frequency.
SWD uses two pins, either two of the JTAG pins (TMS and TCK)
or the USBIO D+ and D– pins. The USBIO pins are useful for in
system programming of USB solutions that would otherwise
require a separate programming connector. One pin is used for
the data clock and the other is used for data input and output.
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 μs (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined acquire sequence of
1s and 0s. If the NVL latches are set for SWD (see Section 5.5),
this sequence need not be applied to the JTAG pin pair. The
acquire sequence must always be applied to the USB pin pair.
SWD is used for debugging or for programming the flash
memory.
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
Figure 9-2. SWD Interface Connections between PSoC 3 and Programmer
Host Programmer
V_DD
PSoC 3
V_DD
V_DDD, V_DDA, V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3 ^{1, 2, 3}
SWDCK
SWDIO
XRES
SWDCK (P1[1] or P15[7])
SWDIO (P1[0] or P15[6])
XRES or P1[2] ^{3, 4}
GND
GND
V_SSD, V_SSA
1 _{The voltage levels of the Host Programmer and the PSoC 3 voltage domains involved in Programming}
should be the same. XRES pin (XRES_N or P1[2]) is powered by V_DDIO1. The USB SWD pins are
powered by V_DDD. So for Programming using the USB SWD pins with XRES pin, the V_DDD, V_DDIO1 of
PSoC 3 should be at the same voltage level as Host V_DD. Rest of PSoC 3 voltage domains ( V_DDA, V_DDIO0,
V_DDIO2, V_DDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are
powered by V_DDIO1. So V_DDIO1 of PSoC 3 should be at same voltage level as host V_DD for Port 1 SWD
programming. Rest of PSoC 3 voltage domains ( V_DDD, V_DDA, V_DDIO0, V_DDIO2, V_DDIO3) need not be at the same
voltage level as host Programmer.
2 _{Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.}
3 _{For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have}
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
4 _{P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For}
devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-
pin devices, but use dedicated XRES pin for rest of devices.
Document Number: 001-56955 Rev. *Y
Page 64 of 128