CY7C955 Datasheet, PDF (62/78 Pages) Cypress Semiconductor – AX™ ATM-SONET/SDH Transceiver

PRELIMINARY
Switching Characteristics Over the Operating Range (continued)
Parameter
Description
t_HWL
t_HWD
t_HWA
t_PW
Write to Address Latch Enable Hold
Write to Data Invalid Hold
Write to Address Invalid Hold
Write Pulse Width
Line Interface (Receive Side) Timing
t_R
RRCLK± Duty Cycle
19.44 MHz or 6.48 MHz
(RBYP = 0)
f_R
RRCLK± Frequency Tolerance^{[8, 9]}
t_SDC
RXD± Stable to RRCLK± Rising Edge Setup Time. R_BYP = 1
t_HCD
RRCLK± State Change to RXD Unstable Hold Time. R_BYP = 1
Receive Side Alarm Timing
t_DCR
RCLK HIGH to RALM or RFP Valid Delay
Line Interface (Transmit Side) Timing
t_T
TRCLK± Duty Cycle
19.44 MHz or 6.48 MHz
(TBYP = 0)
f_T
t_DTO
t_DTD
TRCLK± Frequency Tolerance
TCLK HIGH to TFPO Valid Delay
TXC± LOW to TXD± Valid Delay
UTOPIA Interface (Receive Side) Timing [TSEN = 0]
f_RF
RFCLK Frequency
t_RF
RFCLK Duty Cycle
t_SRC
RRDENB Stable to RFCLK HIGH Set-Up
t_HCR
RFCLK HIGH to RRDENB Unstable Hold
t_DCD
RFCLK HIGH to RSOC / RCA / RXPRTY / RDAT [7:0] Valid Delay
UTOPIA Interface (Receive Side) Timing [TSEN = 1]
f_RF
RFCLK Frequency
t_RF
RFCLK Duty Cycle
t_SRC
RRDENB Stable to RFCLK HIGH Set-Up
t_HCR
RFCLK HIGH to RRDENB Unstable Hold
t_DCA
RFCLK HIGH to RCA Valid Delay
t_DCD
RFCLK HIGH to RSOC / RXPRTY / RDAT [7:0] Valid Delay
t_DCT
RFCLK HIGH to RSOC / RXPRTY / RDAT [7:0] Three-state Delay
GFC (RECEIVE SIDE) TIMING
t_DCG
RCLK HIGH to RGFC / RCP Valid Delay
UTOPIA INTERFACE (TRANSMIT SIDE) TIMING
f_TF
TFCLK Frequency
t_TF
TFCLK Duty Cycle
t_STC
TWRENB / TDAT[7:0] / TXPRTY / TSOC Stable to TFCLK HIGH Set-Up
Notes:
8. Not Tested.
9. See description on Receive Clock Recovery (RCR) page 10
Min.
5
5
5
40
30
−250
2
1
2
30
–250
3
–2
40
10
1
2
40
10
1
2
2
2
−1
40
10
CY7C955
Max.
70
250
20
70
250
20
2
33
60
20
33
60
20
20
20
10
33
60
Unit
ns
ns
ns
ns
%
ppm
ns
ns
ns
%
ppm
ns
ns
MHz
%
ns
ns
ns
MHz
%
ns
ns
ns
ns
ns
ns
MHz
%
ns
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