CY7C955 Datasheet, PDF (29/78 Pages) Cypress Semiconductor – AX™ ATM-SONET/SDH Transceiver

PRELIMINARY
CY7C955
REG − 14H
BIT POSITION
7
6
5
4
3
2
1
0
Transmit Section Overhead Processor Control Register
NAME
Unused
DS
Unused
Unused
Unused
Unused
Unused
LAIS
READ/WRITE
DEFAULT
R/W
0
R/W
0
DS
This bit controls whether SONET scrambling is done to the transmit data stream.
0: Scrambling is performed.
1: Scrambling is not performed.
LAIS
This bit controls whether line Alarm Indication Signal (AIS) is being inserted into the transmit data stream.
1: All bits in the SONET frame (excluding the section overhead) are converted to a 1 prior to SONET scrambling. This
operation begins immediately at the next frame boundary.
0: No line AIS is transmitted.
REG − 15H
BIT POSITION
7
6
5
4
3
2
1
0
Transmit Section Overhead Processor Error Insertion Register
NAME
Unused
Unused
Unused
Unused
Unused
DLOS
DBIP8
DFP
READ/WRITE
DEFAULT
R/W
0
R/W
0
R/W
0
DLOS
This bit generates a continuous loss of signal error in the transmit data stream.
0: Normal operation.
1: TXD transmits all zeros.
DBIP8
This bit generates a continuous section BIP−8 (B1) error in the transmit data stream.
0: Normal operation.
1: B1 byte is inverted.
DFP
This bit generates a framing byte error in the transmit data stream.
0: Normal operation.
1: The most significant bit of the section overhead framing byte is converted from 1 to 0. In other words, F6H becomes H
in the first A1 byte of the section overhead.
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