CY7C955 Datasheet, PDF (50/78 Pages) Cypress Semiconductor – AX™ ATM-SONET/SDH Transceiver

PRELIMINARY
CY7C955
REG − 55H
BIT POSITION
7
6
5
4
3
2
1
0
Receive ATM Cell Processor Uncorrectable HCS Error Count Register
NAME
READ/WRITE
UHCS[7]
R
UHCS[6]
R
UHCS[5]
R
UHCS[4]
R
UHCS[3]
R
UHCS[2]
R
UHCS[1]
R
UHCS[0]
R
DEFAULT
UHCS[7:0]
Reg−54H and Reg−55H will load the number of uncorrectable HCS errors from an internal counter approximately 200 ns after
a write operation is done to Reg−54H, Reg−55H, or Reg−00H. At that time (200 ns after the write operation), this register is
updated and the internal uncorrectable HCS error counter is reset to zero to begin another round of error accumulation. Reading
Reg−54H and Reg.–55H after the write yields the number of uncorrectable HCS errors accumulated since the counter was last
reset, if overflow has not occurred.
REG − 56H
BIT POSITION
7
6
5
4
3
2
1
0
Receive ATM Cell Processor Receive Cell Counter Register
NAME
RCELL[7]
RCELL[6]
RCELL[5]
RCELL[4]
RCELL[3]
RCELL[2]
RCELL[1]
RCELL[0]
READ/WRITE
R
R
R
R
R
R
R
R
DEFAULT
RCELL[18:0]
Reg−56H, Reg−57H, and Reg−58H will load the number of cells received from an internal counter approximately 200ns after
a write operation is done to Reg−54H, Reg−55H, Reg−56H, Reg−57H, Reg−58H, or Reg−00H. At that time (200ns after the
write operation), this register is updated and the internal receive cell counter is reset to zero to begin another round of accu-
mulation. Reading Reg−56H, Reg−57H, and Reg−58H after the write yields the number of cells received since the counter was
last reset, if overflow has not occurred.
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