CY7C955 Datasheet, PDF (1/78 Pages) Cypress Semiconductor – AX™ ATM-SONET/SDH Transceiver

PRELIMINARY
CY7C955
AX™ ATM-SONET/SDH Transceiver
Features
• WAN and LAN ATM physical layer device
• Provides complete physical layer transport of ATM cells
at:
— STS−3c/ STM−1 rate of 155.52 MHz
— STS−1 rate of 51.84 MHz
• Compliant with ATM Forum User Network Interface 3.1
specification
• UTOPIA ATM interface
• ATM cell processing including:
— HEC generation/verification
— Cell scrambling/descrambling
— Rate adaption/idle cell filtering
— Local Flow Control
— Cell alignment
• SONET frame processing including:
— Compliant with Bellcore GR−253, I.432,
T1.105, and G.709 for Jitter Tolerance and Jitter
Generation
— Frame generation/recovery
— SONET scrambling/descrambling
— Frequency justification/pointer processing
• Complete line interface including:
— Clock and data recovery
— Transmit timing derived from receiver or byte-rate
source
— SONET compliant PLL
— 100K PECL compatible I/O
• Alarm indications including:
— Loss Of Signal
— Out Of Frame, Loss Of Frame
— Line Far End Receive Failure
— Line Alarm Indication Signal
— B1 Parity Error
— Loss Of Cell Alignment
— Loss Of Receive Data
• Controller interface for internal interrupt and
configuration registers including:
— Error monitoring
— Status indication
— Device configuration
• 0.65µ Low Power CMOS
• 128-pin PQFP
Functional Description
The Cypress Semiconductor CY7C955 is a Transceiver chip
designed to carry ATM cells across SONET/SDH systems.
On the transmit side, ATM cells coming from the Utopia inter-
face are being mapped into SONET/SDH frames and then se-
rialized for transmission over fiber or twisted pair (through an
optical module or an equalizer chip).
On the receive side, serial SONET/SDH datastreams coming
from an optical module or an equalizer chip are being recov-
ered by the intergrated clock and data recovery phase-locked
loop, framed, processed, and presented as parallel ATM cells
on the Receive Utopia Interface.
The CY7C955 can be used in a Network Interface Card (NIC)
design to connect the segmentation and Reassembly (SAR)
chip to the optical modules or equalizer chip.
The CY7C955 can also be used in work group or enterprise
switches to connect the I/O FIFOs of the switch fabric to the
optical module or equalizer in the interface boards.
The applications of the CY7C955 include adapters, switches,
routers, hubs, and proprietary systems.
TABLE OF CONTENTS
Features
1
Functional Description
1
Pin Descriptions
2
Pin Configuration
7
Description
8
Transmit Section
8
Receive Section
10
Controller Interface (CI)
12
Loopback Operation
16
SONET Overhead Description
17
CY7C955 Register Map
18
Electrical Characteristics
60
Capacitance
61
AC Test Loads and Waveforms
61
Switching Characteristics
61
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 29, 1999