CY7C955 Datasheet, PDF (37/78 Pages) Cypress Semiconductor – AX™ ATM-SONET/SDH Transceiver

PRELIMINARY
CY7C955
REG − 31H
BIT POSITION
7
6
5
4
3
2
1
0
Receive Path Overhead Processor Register
NAME
PSLI
Unused
LOPI
Unused
PAISI
PRDII
BIPEI
FEBEI
READ/WRITE
R
R
R
R
R
R
DEFAULT
PSLI
This is the Path Signal Label (PSL) register interrupt bit. This bit resets when Reg−31H is being read.
0: No change in the path signal label since Reg−31H was last read.
1: There is a change in the path signal label since Reg−31H was last read.
LOPI
This is the Loss of Pointer (LOP) interrupt bit. This bit resets when Reg−31H is being read.
0: No change in the loss of pointer state since Reg−31H was last read.
1: There is a change in the loss of pointer state since Reg−31H was last read.
PAISI
This is the path Alarm Indication Signal (AIS) interrupt bit. This bit resets when Reg−31H is being read.
0: No change in the path alarm indication signal since Reg−31H was last read.
1: There is a change in the path alarm indication signal since Reg−31H was last read.
PRDII
This is the path Far-End Receive Failure (RDI) alarm interrupt bit. This bit resets when Reg−31H is being read.
0: No change in the path far-end receive failure alarm since Reg−31H was last read.
1: There is a change in the path far-end receive failure alarm since Reg−31H was last read.
BIPEI
This is the BIP−8 (B3) error interrupt bit. This bit resets when Reg−31H is being read.
0: No BIP−8 (B3) error detected since Reg−31H was last read.
1: BIP−8 (B3) error has been detected since Reg−31H was last read.
FEBEI
This is the path Far-End Block Error (FEBE) interrupt bit. This bit resets when Reg−31H is being read.
0: No path far-end block error detected since Reg−31H was last read.
1: Path far-end block error has been detected since Reg−31H was last read.
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