W48S87-72 Datasheet, PDF (6/19 Pages) Cypress Semiconductor – Desktop/Notebook Frequency Generator

W48S87-72
Writing Data Bytes
Each bit in the data bytes control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 0–7.
Table 5 details additional frequency selections that are avail-
able through the serial data interface.
Table 4. Data Bytes 0–7 Serial Configuration Map
Table 6 details the select functions for Byte 0, bits 1 and 0.
Affected Pin
Bit Control
Bit(s) Pin No. Pin Name
Control Function
0
1
Default
Data Byte 0
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
Refer to Table 5
0
5
--
--
SEL_4
Refer to Table 5
0
4
--
--
SEL_3
Refer to Table 5
0
3
23
48/24MHZ 48-/24-MHz Clock Output Frequency Selection 24 MHz
48 MHz
0
2
22
48/24MHZ 48-/24-MHz Clock Output Frequency Selection 24 MHz
48 MHz
0
1–0
--
--
Bit 1 Bit 0
Function (See Table 6 for function details)
00
0
0
Normal Operation
0
1
Test Mode
1
0
Spread Spectrum On
1
1
All Outputs Three-stated
Data Byte 1
7
23
48/24MHZ Clock Output Disable
Low
Active
1
6
22
48/24MHZ Clock Output Disable
Low
Active
1
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
38
CPU3 Clock Output Disable
Low
Active
1
2
39
CPU2 Clock Output Disable
Low
Active
1
1
41
CPU1 Clock Output Disable
Low
Active
1
0
42
CPU0 Clock Output Disable
Low
Active
1
Data Byte 2
7
--
--
(Reserved)
--
--
0
6
8
PCI_F Clock Output Disable
Low
Active
1
5
16
PCI5
Clock Output Disable
Low
Active
1
4
14
PCI4
Clock Output Disable
Low
Active
1
3
13
PCI3
Clock Output Disable
Low
Active
1
2
12
PCI2
Clock Output Disable
Low
Active
1
1
11
PCI1
Clock Output Disable
Low
Active
1
0
9
PCI0
Clock Output Disable
Low
Active
1
Data Byte 3
7
26
SDRAM7 Clock Output Disable
Low
Active
1
6
27
SDRAM6 Clock Output Disable
Low
Active
1
5
29
SDRAM5 Clock Output Disable
Low
Active
1
4
30
SDRAM4 Clock Output Disable
Low
Active
1
3
32
SDRAM3 Clock Output Disable
Low
Active
1
2
33
SDRAM2 Clock Output Disable
Low
Active
1
1
35
SDRAM1 Clock Output Disable
Low
Active
1
0
36
SDRAM0 Clock Output Disable
Low
Active
1
6